JPH01268043A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH01268043A JPH01268043A JP9720388A JP9720388A JPH01268043A JP H01268043 A JPH01268043 A JP H01268043A JP 9720388 A JP9720388 A JP 9720388A JP 9720388 A JP9720388 A JP 9720388A JP H01268043 A JPH01268043 A JP H01268043A
- Authority
- JP
- Japan
- Prior art keywords
- aluminum
- wiring
- melting
- thickness
- point metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 19
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 19
- 229910000838 Al alloy Inorganic materials 0.000 claims abstract description 7
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 7
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 6
- 239000003870 refractory metal Substances 0.000 claims 2
- 229910052751 metal Inorganic materials 0.000 abstract description 10
- 239000002184 metal Substances 0.000 abstract description 10
- 229910052750 molybdenum Inorganic materials 0.000 abstract description 7
- 239000011733 molybdenum Substances 0.000 abstract description 7
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 abstract description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 6
- 230000005012 migration Effects 0.000 abstract description 5
- 238000013508 migration Methods 0.000 abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052710 silicon Inorganic materials 0.000 abstract description 3
- 239000010703 silicon Substances 0.000 abstract description 3
- 239000000758 substrate Substances 0.000 abstract description 3
- 238000001312 dry etching Methods 0.000 abstract description 2
- 238000000034 method Methods 0.000 abstract 1
- 238000002844 melting Methods 0.000 description 7
- 238000009792 diffusion process Methods 0.000 description 3
- 230000008018 melting Effects 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 150000002751 molybdenum Chemical class 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特に用いられる配線構造に
関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a wiring structure used therein.
従来、半導体集積回路装置の配線にはアルミニウムある
いはアルミニウムとシリコンの合金が用いられてきてい
る。Conventionally, aluminum or an alloy of aluminum and silicon has been used for wiring in semiconductor integrated circuit devices.
上述した従来のアルミニウムあるいはアルミニウム合金
は微細加工が非常に困難であり又エレクトロ・マイグレ
ーションあるいはストレスマイグレーションに極めて弱
いという欠点がある。The above-mentioned conventional aluminum or aluminum alloy has the disadvantage that it is very difficult to microfabricate and is extremely susceptible to electromigration or stress migration.
本発明の半導体集積回路は、高融点金属あるいは高融点
金属シリサイド配線の側壁あるいは表面カアルミニウム
あるいはアルミニウム合金テ覆ワれている配線を有して
いる。The semiconductor integrated circuit of the present invention has wiring in which the sidewalls or surfaces of high-melting point metal or high-melting point metal silicide wiring are covered with aluminum or aluminum alloy.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例を示す断面図である。FIG. 1 is a sectional view showing an embodiment of the present invention.
１００はｎ型Ｓｔ基板、１０１は接合深さが０．３μｍ
のＰ”拡散層又１０２は膜厚５０００人のシリコン酸化
膜である。１０３は膜厚５０００人のモリブデン配線で
配線幅１μｍである。１０４はアルミニウムであり、モ
リブデン配線１０３を形成後、２０００人のアルミニウ
ムをシリコンウェハー全体に被着し、異方性のドライエ
ツチングでエッチバックし、アルミニウム１０４をモリ
ブデン配線の側壁に残存させたものである。このモリブ
デン配線１０３は０．８Ｘ０．８（μｍ）２のフンタク
ト孔１０５を介してＰ＋拡散層１０１に接続されている
。100 is an n-type St substrate, 101 has a junction depth of 0.3 μm
The P" diffusion layer or 102 is a silicon oxide film with a thickness of 5,000 layers. 103 is a molybdenum wiring with a thickness of 5,000 layers and a wiring width of 1 μm. 104 is aluminum, and after forming the molybdenum wiring 103, it is a silicon oxide film with a thickness of 5,000 layers. aluminum is deposited on the entire silicon wafer and etched back by anisotropic dry etching, leaving aluminum 104 on the side walls of the molybdenum wiring.This molybdenum wiring 103 has a diameter of 0.8 x 0.8 (μm). It is connected to the P+ diffusion layer 101 via the contact hole 105 of No. 2.
第２図は、本発明の他の実施例を示す断面図である。２
００は、膜厚５０００人のシリコン酸化膜、２０１はタ
ングステンで膜厚１μｍ配線幅は１μｍである。２０２
は膜厚２０００人のアルミニウムで、タングステン配線
２０１に選択的にアルミニウムを被着して形成したもの
である。FIG. 2 is a sectional view showing another embodiment of the invention. 2
00 is a silicon oxide film with a thickness of 5000, and 201 is a tungsten film with a thickness of 1 μm and a wiring width of 1 μm. 202
The film is made of aluminum having a thickness of 2000 nm, and is formed by selectively depositing aluminum on the tungsten wiring 201.
このように、本発明では微細加工の容易な高融点金属あ
るいは高融点金属シリサイドの配線の側面するいは表面
をアルミニウムあるいはアルミニウム合金で覆う“ので
、微細な配線パターンが形成可能であり、さらに高融点
金属あるいは、そのシリサイド配線の抵抗が高くても、
側壁あるいは表面を覆うアルミニウムあるいはアルミニ
ウム合金により配線の抵抗を十分に下げることが可能で
ある。さらに高融点金属あるいは高融点金属シリサイド
はエレクトロマイグレーションあるいはストレスマイグ
レーション耐性が十分に大きいという長所も併せて有す
る。このように本発明により、微細で、かつ抵抗が小さ
く、さらにエレク）＋＝ｙマイグレーション、ストレス
マイグレーション耐性のある配線を使用する半導体・集
積回路装置を提供できるという効果がある。As described above, in the present invention, the sides or surface of wiring made of high-melting point metal or high-melting point metal silicide, which can be easily microfabricated, is covered with aluminum or aluminum alloy, so it is possible to form fine wiring patterns. Even if the resistance of the melting point metal or its silicide wiring is high,
It is possible to sufficiently lower the resistance of the wiring by covering the sidewalls or surface with aluminum or aluminum alloy. Furthermore, high melting point metals or high melting point metal silicides also have the advantage of having sufficiently high resistance to electromigration or stress migration. As described above, the present invention has the advantage that it is possible to provide a semiconductor/integrated circuit device that uses wiring that is fine, has low resistance, and is resistant to electronic migration and stress migration.
第１図および第２図はそれぞれ本発明の実施例を示す断
面図である。
１００・・・・・・ｎ型Ｓｉ基板、１０１・・・・・・
Ｐ＋拡散層、１０２・・・・・・シリコン酸化膜、１０
３・・・・・・モリブデン、１０４・・・・・・アルミ
ニウム、１０５・・・・・・コンタクト孔、２００・・
・・・・シリコン酸化膜、２０１・・・・・・タングス
テン、２０２・・・・・・アルミニウム。
代理人 弁理士 内 原 晋FIG. 1 and FIG. 2 are sectional views each showing an embodiment of the present invention. 100...n-type Si substrate, 101...
P+ diffusion layer, 102...Silicon oxide film, 10
3... Molybdenum, 104... Aluminum, 105... Contact hole, 200...
... Silicon oxide film, 201 ... Tungsten, 202 ... Aluminum. Agent Patent Attorney Susumu Uchihara
Claims (1)
あるいは表面がアルミニウムあるいはアルミニウムの合
金で覆れていることを特徴とする半導体装置。A semiconductor device characterized in that a side wall or surface of a refractory metal or a refractory metal silicide wiring is covered with aluminum or an aluminum alloy.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9720388A JPH01268043A (en) | 1988-04-19 | 1988-04-19 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9720388A JPH01268043A (en) | 1988-04-19 | 1988-04-19 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01268043A true JPH01268043A (en) | 1989-10-25 |
Family
ID=14186054
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9720388A Pending JPH01268043A (en) | 1988-04-19 | 1988-04-19 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01268043A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5126283A (en) * | 1990-05-21 | 1992-06-30 | Motorola, Inc. | Process for the selective encapsulation of an electrically conductive structure in a semiconductor device |
-
1988
- 1988-04-19 JP JP9720388A patent/JPH01268043A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5126283A (en) * | 1990-05-21 | 1992-06-30 | Motorola, Inc. | Process for the selective encapsulation of an electrically conductive structure in a semiconductor device |
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