JPH01268191A - Inspecting method for wiring net of ceramic board - Google Patents
Inspecting method for wiring net of ceramic boardInfo
- Publication number
- JPH01268191A JPH01268191A JP9775588A JP9775588A JPH01268191A JP H01268191 A JPH01268191 A JP H01268191A JP 9775588 A JP9775588 A JP 9775588A JP 9775588 A JP9775588 A JP 9775588A JP H01268191 A JPH01268191 A JP H01268191A
- Authority
- JP
- Japan
- Prior art keywords
- conductor
- circuit
- board
- resistor
- terminals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
- G01R31/2805—Bare printed circuit boards
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
プリント板に使用される多層のセラミック基板において
、焼成積層後に基板の配線ネットの断線、ショートを検
査する検査方法に関し、配線ネットの検査を基板片面の
プロービィングで簡単化でき、断線及びショートの検査
を同時に行うことを目的とし、
セラミック基板の一方の面の電源と他の導体用端子を、
抵抗を介して回路接続し、セラミック基板の他方の面の
電源と他の導体用端子をプロービィングして、抵抗値に
より断線、ショートを検査するように構成する。[Detailed Description of the Invention] [Summary] Regarding an inspection method for inspecting disconnections and short circuits of wiring nets on a multilayer ceramic substrate used for printed boards after firing and lamination, the wiring net is inspected by probing one side of the board. For the purpose of simplifying the test and simultaneously inspecting disconnections and short circuits, the power supply and other conductor terminals on one side of the ceramic board are
The circuit is connected through a resistor, and the power supply and other conductor terminals on the other side of the ceramic substrate are probed to check for disconnections and shorts based on the resistance value.
本発明は、プリント板に使用される多層のセラミック基
板において、焼成積層後に基板の配線ネットの断線、シ
ョートを検査する検査方法に関する。The present invention relates to an inspection method for inspecting disconnections and short circuits in wiring nets of a multilayer ceramic substrate used in a printed board after firing and lamination.
近年、プリント板の実装において高密度化、高速化の要
求が著しく、この対策の1つとして基板の高多層化が考
えられている。高多層化基板用材料の特性としては、寸
法変化やそりが小さいこと、電気及び熱的特性が良いこ
と、熱膨張が小さいこと、半田耐熱性に優れていること
が要求され、この点で有機材に代わりセラミックを用い
た実用化が期待されている。In recent years, there has been a significant demand for higher densities and higher speeds in mounting printed circuit boards, and one way to counter this is to increase the number of layers in the board. Materials for highly multilayered boards are required to have small dimensional changes and warpage, good electrical and thermal properties, small thermal expansion, and excellent soldering heat resistance, and are advantageous in this respect. There are high expectations for the practical use of ceramics in place of materials.
セラミック基板の多層化方法には種々提案されているが
、そのうちの積層法ではグリーンシートの絶縁層に導体
パターンを印刷し、これを何層にも重ねて圧着した状態
で焼成することにより一体的に積層される。従って、こ
のセラミ・ンク基板では有機材基板のように、すべての
層に貫通したスルーホールによる配線ネンl−が無い。Various methods have been proposed for multi-layering ceramic substrates, among which the lamination method prints a conductor pattern on the insulating layer of a green sheet, stacks these in layers, presses them together, and fires them. Laminated on. Therefore, unlike organic substrates, this ceramic ink substrate does not have wiring lines formed by through holes penetrating all layers.
このため、積層化後の配線ネットのプローブによる検査
ではスルーホールを利用できず、新たな検査方法を確立
することが要求される。For this reason, through holes cannot be used to inspect the wiring net after lamination using a probe, and a new inspection method is required to be established.
そこで、従来上記セラミック基板の配線ネット検査は第
2図のように行われている。即ち、セラミック基板1は
例えば4つのセラミックの絶縁層2aないし2dを積層
した状態において、各層間にviaに導体ペーストを詰
めて成る導体パターンが設けられる。ここで、絶縁層2
cと2dの間には電源導体3aが設シフられ、この導体
3aと接続した導体3b、30、非接続の導体3 d、
3eが基板1の表面]aと裏面1bに出ている。Therefore, conventionally, the wiring net inspection of the ceramic substrate is carried out as shown in FIG. That is, in the ceramic substrate 1, for example, four ceramic insulating layers 2a to 2d are laminated, and a conductive pattern is provided between each layer by filling vias with conductive paste. Here, insulating layer 2
A power supply conductor 3a is installed between c and 2d, conductors 3b and 30 are connected to this conductor 3a, and conductors 3d and 3d are not connected.
3e is exposed on the front surface]a and the back surface 1b of the substrate 1.
そして、各導体3bないし3eは表面1aで各集積回路
部品の端子4aないし4gに、裏面1bで各入出力ビン
の端子5aないし5dに接続している。Each conductor 3b to 3e is connected to a terminal 4a to 4g of each integrated circuit component on the front side 1a, and to a terminal 5a to 5d of each input/output bin on the back side 1b.
そこで、上記セラミック基板1において表面1aの端子
4cと裏面1bの端子5aにプローブ6.7を接して、
導体3bの断線検査を行う。以下、同様にして各導体3
cないし3eの配線不。Therefore, in the ceramic substrate 1, a probe 6.7 is placed in contact with the terminal 4c on the front surface 1a and the terminal 5a on the back surface 1b.
Conductor 3b is inspected for disconnection. Hereafter, each conductor 3
No wiring for c or 3e.
トをプロービィングして検査するものである。This test is performed by probing and inspecting the target.
〔発明が解決しようとする課題]
ところで、上記従来の検査方法によると、プローブ6.
7を基板1の両面1a、]bに接触配置するため、検査
機の機構が蝮雑化する。また、2つのプローブ6.7の
移動時間等により検査時間が長くなる。一方、かかるブ
ロービイングでは断線検査のみ可能で、ネット間及び電
a導体とのショーI・は検査できない問題がある。[Problems to be Solved by the Invention] By the way, according to the above conventional inspection method, the probe 6.
7 is placed in contact with both surfaces 1a, ]b of the substrate 1, the mechanism of the inspection machine becomes complicated. Furthermore, the inspection time becomes longer due to the time required to move the two probes 6 and 7. On the other hand, there is a problem that such blowby can only test for disconnection, and cannot test for wire breaks between nets or between conductors.
本発明は、かかる問題点に鑑みなされたものであって、
その目的とするところは、配線ネットの検査を基板片面
のブロービイングで簡単化でき、断線及びショートの検
査を同時に行うことができるセラミック基板の配線ネ7
l・検査方法を提供することにある。The present invention was made in view of such problems, and includes:
The purpose of this is to simplify the inspection of wiring nets by blowing one side of the board, and to simultaneously inspect wiring nets on ceramic substrates for disconnections and short circuits.
1. To provide an inspection method.
上記目的を達成するため、本発明の検査方法は、基板の
表、裏面に出ている電源導体を利用し、この電源導体と
他の導体を回路構成して検査するものである。In order to achieve the above object, the inspection method of the present invention utilizes the power supply conductor exposed on the front and back surfaces of the board, and conducts the inspection by configuring the power supply conductor and other conductors into a circuit.
そこで、基板の一方の面の端子を抵抗を介して電源導体
の端子に回路接続する。そして、基板の他方の面の電源
導体と他の導体の端子をプロービィングして抵抗値を読
取り、抵抗値により断線、ショートを検査するものであ
る。Therefore, the terminal on one side of the board is connected to the terminal of the power supply conductor via a resistor. Then, the terminals of the power supply conductor and other conductors on the other side of the board are probed to read the resistance value, and the resistance value is used to check for disconnections and short circuits.
上記方法により、セラミック基板の片面のみのブロービ
イングで検査されることになる。そして、2つの導体の
回路の抵抗値が無限大に増すことで断線が、途中短絡し
て抵抗値が減少することでショートが検査される。According to the above method, only one side of the ceramic substrate is inspected by blowing. Then, the resistance value of the circuit between the two conductors increases to infinity, thereby detecting a break, and the short-circuit occurs midway, reducing the resistance value, thereby detecting a short circuit.
以下、本発明の実施例を図面に基いて説明する。 Embodiments of the present invention will be described below with reference to the drawings.
第1図において、符号1はセラミック基板、2aないし
2dは絶縁層、3aないし3cは電源導体、3d、3e
は人、出力信号の導体、4a、ないし4g及び5aない
し5dは各端子であって、第2図と同様に構成される。In FIG. 1, numeral 1 is a ceramic substrate, 2a to 2d are insulating layers, 3a to 3c are power supply conductors, 3d, 3e
2 is a conductor for output signals, and 4a to 4g and 5a to 5d are terminals, which are constructed in the same manner as in FIG.
そこで、上記基板1の裏面1bの端子5aないし5dが
抵抗8を有する回路9により接続される。そして、この
状態で基板1の表面1aにおいて、例えば端子4aと4
cにプローブ6.7を接触して検査機10により抵抗値
を読取るのである。Therefore, the terminals 5a to 5d on the back surface 1b of the substrate 1 are connected by a circuit 9 having a resistor 8. Then, in this state, on the surface 1a of the substrate 1, for example, the terminals 4a and 4
The resistance value is read by the tester 10 by contacting the probe 6.7 with the probe 6.7.
これにより、電源導体3bと他の導体3dが抵抗8を有
する回路9を介して検査機10に回路接続し、両扉体3
b、3dが同時に検査される。そして、導体3b、3d
の途中が断線していると、抵抗値が無限大になってそれ
が検査できる。また、導体3dと電源導体3a又は3b
との交差点P1又はP2でショートする場合は、抵抗8
が並列の接続状態になってその値が小さくなり、これに
より電源とのショートが検査できる。As a result, the power supply conductor 3b and the other conductor 3d are connected to the inspection machine 10 via the circuit 9 having the resistor 8, and both door bodies 3
b and 3d are inspected simultaneously. And conductors 3b, 3d
If there is a break in the middle of the wire, the resistance value will become infinite and this can be detected. In addition, the conductor 3d and the power supply conductor 3a or 3b
If a short circuit occurs at the intersection P1 or P2, resistor 8
are connected in parallel, their value becomes smaller, and this allows you to check for shorts with the power supply.
以下、同様にしてプローブ6.7の接触位置を変えるこ
とで、配線ネットの各導体の断線、ショートが検査され
る。Thereafter, by changing the contact position of the probe 6.7 in the same manner, each conductor of the wiring net is inspected for disconnection or short circuit.
以上述べてきたように、本発明によれば、高多層のセラ
ミック基板でスルーホールが無い場合でも、基板片面の
ブロービイングで検査することができ、検査機構が簡素
化し、検査時間も短縮化する。As described above, according to the present invention, even in the case of a highly multilayered ceramic substrate without through-holes, it is possible to inspect by blowing one side of the substrate, simplifying the inspection mechanism and shortening the inspection time. .
電源導体を利用して断線のみならずショートも同時に検
査できるので、検査性能が向上する。Since the power supply conductor can be used to simultaneously test for short circuits as well as disconnections, test performance is improved.
抵抗を有する回路を接続するだけであるから、構造が簡
単である。The structure is simple because only a circuit having a resistance is connected.
第1図は本発明の検査方法の実施例を示す図、第2図は
従来の検査状態を示す図である。
図において、
1はセラミック基板、
1aは表面、
lbは裏面、
4a、4c、5a、5bは端子、
8は抵抗を示す。FIG. 1 is a diagram showing an embodiment of the inspection method of the present invention, and FIG. 2 is a diagram showing a conventional inspection state. In the figure, 1 is a ceramic substrate, 1a is a front surface, lb is a back surface, 4a, 4c, 5a, 5b are terminals, and 8 is a resistor.
Claims (1)
の導体用端子(5a、5b)を、抵抗(8)を介して回
路接続し、 セラミック基板(1)の他方の面(1a)の電源と他の
導体用端子(4a、4c)をプロービィングして、抵抗
値により断線、ショートを検査することを特徴とするセ
ラミック基板の配線ネット検査方法。[Claims] A power supply and other conductor terminals (5a, 5b) on one side (1b) of the ceramic substrate (1) are connected in a circuit via a resistor (8), A method for inspecting a wiring net for a ceramic substrate, which comprises probing the power source and other conductor terminals (4a, 4c) on the other surface (1a) to inspect for disconnections and short circuits based on resistance values.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9775588A JPH01268191A (en) | 1988-04-20 | 1988-04-20 | Inspecting method for wiring net of ceramic board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9775588A JPH01268191A (en) | 1988-04-20 | 1988-04-20 | Inspecting method for wiring net of ceramic board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01268191A true JPH01268191A (en) | 1989-10-25 |
Family
ID=14200697
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9775588A Pending JPH01268191A (en) | 1988-04-20 | 1988-04-20 | Inspecting method for wiring net of ceramic board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01268191A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007305674A (en) * | 2006-05-09 | 2007-11-22 | Denso Corp | Component built-in board and wiring defect inspection method thereof |
| KR100891531B1 (en) * | 2007-09-10 | 2009-04-03 | 주식회사 하이닉스반도체 | Pattern misalignment detection device |
-
1988
- 1988-04-20 JP JP9775588A patent/JPH01268191A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007305674A (en) * | 2006-05-09 | 2007-11-22 | Denso Corp | Component built-in board and wiring defect inspection method thereof |
| KR100891531B1 (en) * | 2007-09-10 | 2009-04-03 | 주식회사 하이닉스반도체 | Pattern misalignment detection device |
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