JPH03219694A - Multilayer wiring board and its inspection method - Google Patents
Multilayer wiring board and its inspection methodInfo
- Publication number
- JPH03219694A JPH03219694A JP1520790A JP1520790A JPH03219694A JP H03219694 A JPH03219694 A JP H03219694A JP 1520790 A JP1520790 A JP 1520790A JP 1520790 A JP1520790 A JP 1520790A JP H03219694 A JPH03219694 A JP H03219694A
- Authority
- JP
- Japan
- Prior art keywords
- board
- power supply
- multilayer wiring
- wiring board
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000007689 inspection Methods 0.000 title claims abstract description 25
- 238000000034 method Methods 0.000 title claims description 8
- 238000005259 measurement Methods 0.000 claims abstract description 16
- 238000012360 testing method Methods 0.000 claims description 15
- 230000000149 penetrating effect Effects 0.000 claims description 10
- 238000009413 insulation Methods 0.000 claims description 6
- 239000000758 substrate Substances 0.000 description 7
- 239000011230 binding agent Substances 0.000 description 4
- 229920002037 poly(vinyl butyral) polymer Polymers 0.000 description 2
- 239000000843 powder Substances 0.000 description 2
- 239000002002 slurry Substances 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- ZNQVEEAIQZEUHB-UHFFFAOYSA-N 2-ethoxyethanol Chemical compound CCOCCO ZNQVEEAIQZEUHB-UHFFFAOYSA-N 0.000 description 1
- 239000005456 alcohol based solvent Substances 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000005388 borosilicate glass Substances 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000007606 doctor blade method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004898 kneading Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000011812 mixed powder Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、基板内部の電源もしくは接地層と接続される
電源・接地スルーホールと表面から裏面まで貫通する信
号スルーホールとを有する多層配線基板およびその検査
方法に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a multilayer wiring board having a power supply/ground through hole connected to a power supply or ground layer inside the board, and a signal through hole penetrating from the front surface to the back surface. and its testing method.
従来のこの種の多層配線基板は、第２図に示すように多
層配線基板２１の表面がら裏面まで貫通した信号スルー
ホール２５と基板２１の内部の接地層２２に接続された
接地スルーホール２６と基板２１の内部のＡ電源層２３
に接続されたＡ電源スルーホール２７と基板２１の内部
のＢ電源層２４に接続されたＢ電源スルーホール２８と
を備えていた。A conventional multilayer wiring board of this type has a signal through hole 25 penetrating from the front surface to the back surface of a multilayer wiring board 21 and a ground through hole 26 connected to a ground layer 22 inside the board 21, as shown in FIG. A power layer 23 inside the substrate 21
It had an A power supply through hole 27 connected to the B power supply layer 24 inside the substrate 21, and a B power supply through hole 28 connected to the B power supply layer 24 inside the substrate 21.
また、このような従来の多層配線基板の信号スルーホー
ルのシロートの検査は各信号スルーホールの８憬を測定
する方法が用いられていた。Further, in order to inspect the slope of the signal through-holes in such a conventional multilayer wiring board, a method of measuring 8 points of each signal through-hole has been used.
上述した従来の多層配線基板では、信号スルーホールの
ショートの検査において各信号スルーホールの容量を測
定するため、信号スルーホールの個数が多くなると検査
工数が非常に多くなってしまう。また、信号スルーホー
ルのオープン検査に至っては信号スルーホール容量が小
さい為、検出が不可能であった。そのため基板表面と裏
面の両面から導通を確認する方法が用いられるが検査工
数が膨大となってしまうという問題がある。In the conventional multilayer wiring board described above, the capacitance of each signal through hole is measured when inspecting for short circuits in the signal through holes, so as the number of signal through holes increases, the number of inspection steps increases significantly. Furthermore, when it came to inspecting open signal through holes, detection was impossible because the signal through hole capacity was small. For this reason, a method is used in which continuity is confirmed from both the front and back surfaces of the substrate, but there is a problem in that the number of inspection steps becomes enormous.
本発明は、基板内部の電源もしくは接地層と接続される
電源・接地スルーホールと、前記基板の表面から裏面ま
で貫通する信号スルーホールとを有する多層配線基板に
おいて、全ての前記信号スルーホールは前記基板の表面
および裏面に設けた検査パターンにより直列に接続され
たことを特徴とする。The present invention provides a multilayer wiring board having power supply/ground through holes connected to a power supply or ground layer inside the board, and signal through holes penetrating from the front surface to the back surface of the board, in which all the signal through holes are connected to the They are characterized in that they are connected in series by inspection patterns provided on the front and back surfaces of the board.
本発明は、基板内部の電源もしくは接地層と接続される
電源・接地スルーホールと、前記基板の表面から裏面ま
で貫通する信号スルーホールとを有する多層配線基板に
おいて、前記基板内部の電源および接地層はそれぞれ前
記基板の表面または裏面に電気的に接続された電源・接
地測定パッドを有し、全ての前記信号スルーホールは前
記基板の表面および裏面に設けた検査パターンにより直
列に接続されたことを特徴とする。The present invention provides a multilayer wiring board having a power supply/ground through hole connected to a power supply or ground layer inside the board, and a signal through hole penetrating from the front surface to the back surface of the board. each has a power/ground measurement pad electrically connected to the front or back side of the board, and all the signal through holes are connected in series by test patterns provided on the front and back sides of the board. Features.
本発明は、基板内部の電源もしくは接地層と接続される
電源・接地スルーホールと、前記基板の表面から裏面ま
で貫通する信号スルーホールとを有する多層配線基板の
検査方法において、前記基板の表面および裏面に全ての
前記信号スルーホールを直列に接続する検査パターンを
設けておいて直列に接続された前記検査パターンの両端
間の抵抗および前記検査パターンと前記基板内部の電源
および接地層との絶縁抵抗を測定した後に前記基板の表
面および裏面から前記検査パターンを削除することを特
徴とする。The present invention provides a method for inspecting a multilayer wiring board having a power supply/ground through hole connected to a power supply or ground layer inside the board, and a signal through hole penetrating from the front surface to the back surface of the board. A test pattern connecting all the signal through-holes in series is provided on the back surface, and resistance between both ends of the test pattern connected in series and insulation resistance between the test pattern and the power supply and ground layer inside the board are provided. The method is characterized in that the test pattern is deleted from the front and back surfaces of the substrate after measuring.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例の多層配線基板を示す切断斜
視図である。FIG. 1 is a cutaway perspective view showing a multilayer wiring board according to an embodiment of the present invention.
多層配線基板１には内部に接地層２とＡ電源層３とＢ電
源層４が設置されており接地層２に接続された接地スル
ーホール６とＡ電源層３に接続されたＡ電源スルーホー
ル７とＢ電源層４に接続されたＢ電源スルーホール８を
有している。そして、多層配線基板１の表面から裏面ま
で貫通した信号スルーホール５は表面検査パターン９と
裏面検査パターン１０によって全て直列に接続されてい
る。A ground layer 2, an A power layer 3, and a B power layer 4 are installed inside the multilayer wiring board 1. A ground through hole 6 is connected to the ground layer 2, and an A power through hole is connected to the A power layer 3. 7 and a B power supply through hole 8 connected to the B power supply layer 4. The signal through holes 5 penetrating the multilayer wiring board 1 from the front surface to the back surface are all connected in series by a front surface inspection pattern 9 and a back surface inspection pattern 10.
また、基板１の表面には接地スルーホール６に接続され
た接地測定バッド１１とＡ電源スルーホール７に接続さ
れたＡ電源測定バッド１２とＢ電源スルーホール８に接
続されたＢ電源測定パッド１３が形成されている。Further, on the surface of the board 1, a ground measurement pad 11 connected to the ground through hole 6, an A power measurement pad 12 connected to the A power supply through hole 7, and a B power measurement pad 13 connected to the B power supply through hole 8 are also provided. is formed.
多層配線基板１を製造するためには、まずグリーンシー
トを作成する必要がある。グリーンシートは原料の無機
粉末であるアルミナとホウケイ酸鉛ガラスの混合粉にバ
インダー（有機樹脂結合剤）としてＰＶＢ （ポリビニ
ルブチラール）を加え、溶剤としてアルコール系溶剤例
えばエチルセルソルブを加え、混合機によって混合Φ混
練を行いバインダーが溶解した溶剤中に無機粉末が均一
に分散した泥しよう（スラリー）を作成する。そして、
次に、得られた泥しようをドクターブレード法等によっ
て有機フィルム等の上に厚さが均一になるように供給し
乾燥させることによって作成した。In order to manufacture the multilayer wiring board 1, it is first necessary to create a green sheet. Green sheet is made by adding PVB (polyvinyl butyral) as a binder (organic resin binder) to a mixed powder of alumina, which is a raw material powder, and lead borosilicate glass, and adding an alcohol-based solvent such as ethyl cellosolve as a solvent. Mixing Φ kneading is performed to create a slurry in which inorganic powder is uniformly dispersed in a solvent in which a binder is dissolved. and,
Next, the obtained slurry was applied onto an organic film or the like using a doctor blade method or the like so that the thickness was uniform, and the film was dried.
つぎに各グリーンシートに上下層間の導通を得るための
スルーホール５．Ｅｌ、７．８を作成し、さらに表面検
査パターン９．接地層２．Ａ電源層３、Ｂ電源層４．裏
面検査パターン１０をスクリーン印刷によって形成した
。そして、これら複数のグリーンシートを第１図に示す
順番によって精度良く積層し熱プレスによって一体化さ
せた後に加熱しバインダーを燃焼・消失（脱バインダー
）させ、その後さらに加熱し焼成を行うことによって多
層配線基板１を得た。Next, each green sheet has through holes 5. to provide electrical continuity between the upper and lower layers. El, 7.8 is created, and a surface inspection pattern 9. Ground layer 2. A power layer 3, B power layer 4. A backside inspection pattern 10 was formed by screen printing. Then, these multiple green sheets are laminated with high accuracy in the order shown in Figure 1, integrated by heat press, heated to burn and eliminate the binder (debinding), and then further heated and fired to form a multi-layered structure. A wiring board 1 was obtained.
次に、本発明の一実施例である多層配線基板１の検査方
法について説明する。Next, a method for inspecting multilayer wiring board 1, which is an embodiment of the present invention, will be described.
まず、接地測定パッド１１．Ａ電源測定パッド１２、Ｂ
電源測定パッド１３各々のパッド間の絶縁抵抗を測定す
る。これによって各電源・接地間の絶縁抵抗を検査でき
る。First, the ground measurement pad 11. A power supply measuring pad 12, B
The insulation resistance between the power supply measurement pads 13 is measured. This allows the insulation resistance between each power source and ground to be tested.
次に、直列接続された表面および裏面検査パターン９，
１０の両端間の抵抗を測定する。信号スルーホール５は
表面および裏面検査パターン９，１０によって直列に接
続されている為信号スルーホール５のオーブンが発生し
ていれば測定抵抗値が著しく大きくなり検出することが
できる。Next, the front and back inspection patterns 9 are connected in series.
Measure the resistance across 10. Since the signal through-holes 5 are connected in series by the front and back surface inspection patterns 9 and 10, if an oven occurs in the signal through-holes 5, the measured resistance value becomes significantly large and can be detected.
次に、表面検査パターン９の接地測定パッド１１間の絶
縁抵抗を測定する。これによって全信号スルーホールと
接地層２とのシロートを検査することができる。同様に
Ａ電源測定バッド１２と表面検査パターン９およびＢ電
源測定パッド１３と表面検査パターン９間を測定するこ
とによって全スルーホール５と各電源層とのシ日−トを
検出することができる。Next, the insulation resistance between the ground measurement pads 11 of the surface inspection pattern 9 is measured. Thereby, the slope between all signal through holes and the ground layer 2 can be inspected. Similarly, by measuring between the A power supply measurement pad 12 and the surface inspection pattern 9 and between the B power supply measurement pad 13 and the surface inspection pattern 9, the dates between all the through holes 5 and each power supply layer can be detected.
以上の検査の後に基板１の表面をｃ−ｃ’Ｃ＃で示す面
まで、基板１の裏面をＤ−Ｄ’Ｄ＃で示す面まで研磨す
る事によって表面および裏面検査パターン９，１０を除
去し、少ない検査工数によって基板検査された多層配線
基板を得ることができる。After the above inspection, the front and back surface inspection patterns 9 and 10 are removed by polishing the front surface of the substrate 1 to the surface indicated by c-c'C# and the back surface of the substrate 1 to the surface indicated by D-D'D#. However, a multilayer wiring board that has been inspected can be obtained with fewer inspection steps.
以上説明したように本発明は、基板内部の電源もしくは
接地層と接続される電源・接地スルーホールと、表面と
裏面を貫通する信号スルーホールとを有する多層配線基
板において、全ての信号スルーホールを基板の表面およ
び裏面で直列に接続する検査パターンを設けておいて検
査パターンの両端の抵抗を測定し、検査パターンと各電
源・接地層間の絶縁抵抗を測定した後に基板の表面およ
び裏面に形成した検査パターンを削除することによって
検査工数を削減した多層配線基板を得ることができる。As explained above, the present invention provides power supply/ground through holes connected to the power supply or ground layer inside the board, and signal through holes penetrating the front and back surfaces of the multilayer wiring board. Test patterns connected in series on the front and back sides of the board were prepared, and the resistance at both ends of the test pattern was measured. After measuring the insulation resistance between the test pattern and each power supply/ground layer, the test patterns were formed on the front and back sides of the board. By eliminating the inspection pattern, a multilayer wiring board with reduced inspection man-hours can be obtained.
ン、１０・・・裏面検査パターン、１１・・・接地測定
パッド、１２・・・Ａ電源測定パッド、１３・・・Ｂ電
源測定パッド。10... Back inspection pattern, 11... Ground measurement pad, 12... A power supply measurement pad, 13... B power supply measurement pad.
Claims (3)
・接地スルーホールと、前記基板の表面から裏面まで貫
通する信号スルーホールとを有する多層配線基板におい
て、全ての前記信号スルーホールは前記基板の表面およ
び裏面に設けた検査パターンにより直列に接続されたこ
とを特徴とする多層配線基板。1. In a multilayer wiring board having power supply/ground through holes connected to the power supply or ground layer inside the board, and signal through holes penetrating from the front surface to the back surface of the board, all of the signal through holes are connected to the front surface and the back surface of the board. A multilayer wiring board characterized by being connected in series by a test pattern provided on the back side.
・接地スルーホールと、前記基板の表面から裏面まで貫
通する信号スルーホールとを有する多層配線基板におい
て、前記基板内部の電源および接地層はそれぞれ前記基
板の表面または裏面に電気的に接続された電源・接地測
定パッドを有し、全ての前記信号スルーホールは前記基
板の表面および裏面に設けた検査パターンにより直列に
接続されたことを特徴とする多層配線基板。2. In a multilayer wiring board having a power supply/ground through hole connected to a power supply or ground layer inside the board, and a signal through hole penetrating from the front surface to the back surface of the board, the power supply and ground layers inside the board are connected to the board, respectively. A multilayer board having a power/ground measurement pad electrically connected to the front or back side of the board, and all of the signal through holes connected in series by test patterns provided on the front and back sides of the board. wiring board.
・接地スルーホールと、前記基板の表面から裏面まで貫
通する信号スルーホールとを有する多層配線基板の検査
方法において、前記基板の表面および裏面に全ての前記
信号スルーホールを直列に接続する検査パターンを設け
ておいて直列に接続された前記検査パターンの両端間の
抵抗および前記検査パターンと前記基板内部の電源およ
び接地層との絶縁抵抗を測定した後に前記基板の表面お
よび裏面から前記検査パターンを削除することを特徴と
する多層配線基板の検査方法。3. In an inspection method for a multilayer wiring board having power/ground through holes connected to a power supply or ground layer inside the board, and signal through holes penetrating from the front surface to the back surface of the board, all After providing a test pattern connecting the signal through holes in series and measuring the resistance between both ends of the test pattern connected in series and the insulation resistance between the test pattern and the power supply and ground layer inside the board. A method for inspecting a multilayer wiring board, comprising removing the inspection pattern from the front and back surfaces of the board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2015207A JP2504252B2 (en) | 1990-01-24 | 1990-01-24 | Inspection method of multilayer wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2015207A JP2504252B2 (en) | 1990-01-24 | 1990-01-24 | Inspection method of multilayer wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03219694A true JPH03219694A (en) | 1991-09-27 |
| JP2504252B2 JP2504252B2 (en) | 1996-06-05 |
Family
ID=11882425
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2015207A Expired - Lifetime JP2504252B2 (en) | 1990-01-24 | 1990-01-24 | Inspection method of multilayer wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2504252B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008218443A (en) * | 2007-02-28 | 2008-09-18 | Micronics Japan Co Ltd | Multilayer wiring board and inspection method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52128558A (en) * | 1976-04-20 | 1977-10-28 | Nippon Electric Co | Method of producing multilayer circuit board |
| JPS5524447A (en) * | 1978-08-09 | 1980-02-21 | Fujitsu Ltd | Method of testing ceramic circuit board |
| JPS60109297A (en) * | 1983-11-18 | 1985-06-14 | 株式会社日立製作所 | Method of producing printed board |
| JPS6340391A (en) * | 1986-08-05 | 1988-02-20 | 日本電気株式会社 | Surface mount printed circuit board |
-
1990
- 1990-01-24 JP JP2015207A patent/JP2504252B2/en not_active Expired - Lifetime
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52128558A (en) * | 1976-04-20 | 1977-10-28 | Nippon Electric Co | Method of producing multilayer circuit board |
| JPS5524447A (en) * | 1978-08-09 | 1980-02-21 | Fujitsu Ltd | Method of testing ceramic circuit board |
| JPS60109297A (en) * | 1983-11-18 | 1985-06-14 | 株式会社日立製作所 | Method of producing printed board |
| JPS6340391A (en) * | 1986-08-05 | 1988-02-20 | 日本電気株式会社 | Surface mount printed circuit board |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008218443A (en) * | 2007-02-28 | 2008-09-18 | Micronics Japan Co Ltd | Multilayer wiring board and inspection method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2504252B2 (en) | 1996-06-05 |
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