JPH01268337A - Interface circuit - Google Patents

Abstract

PURPOSE:To improve the data transfer efficiency by providing a flag for showing whether unprocessed data exists or not, loading the data to a #1 register in case when a #2 register is free, and simultaneously, transferring it to the #2 register. CONSTITUTION:A #1 data store state flag generating means 6 for generating a flag for showing a data store state of a #1 register, a #2 data store state flag generating means 7 for generating a flag for showing a data store state of a #2 register are provided on the #1 register and the #2 register, respectively. In this state, when the #2 data store state flag generating means 7 is '0' for showing a fact that the #2 register 2 is free, data is loaded to the #1 register 1, and simultaneously, transferred to the #2 register. In such a way, the data is read out immediately in series from the #2 register and outputted, therefore, the data transfer efficiency can be improved.

Description

[Detailed Description of the Invention] [Summary] For example, regarding an interface circuit used in a digital signal processing LSI for high-efficiency codec C0DEIC, the purpose of improving data transfer efficiency is to transfer parallel data input via a line. In an interface circuit that writes to the #l register, transfers it to the 12th register, and outputs it as serial data, a #clock generator generates a clock for the #1 register using a load signal and a system clock, and the input load Data storage a of the register using the read end signal from the II2 clock generation means and the +12 data storage status flag.
#1l that generates the #1 data storage status flag indicating the status
A #2 data storage state flag generation unit that generates an I2 data storage state flag indicating the data storage state of the second register using the data storage state flag generating means, the load signal, the read end signal, and the #data storage state flag. Immediately transfer the parallel data written in the #1 register to the #2 register when the #2 register is empty by using the means, the synchronization signal, the read clock, the system clock, and the data storage status flag; It is configured to have 12 clock generation means for generating a clock for the #2 register for reading out serial data.

[Industrial application field]

The present invention relates to, for example, an ink face circuit used in a digital signal processing LSI for a high efficiency codec CODEC.

Usually, high efficiency C0DEC is PCM-C as shown in Figure 4.
0DEC#, interface LSI section 12. It is composed of a digital signal processing section 13 and a RAM 14.

After passing through the PCM-C0D [EC#], analog signals such as audio input to this high-efficiency C0DEC are processed in the digital signal calculation unit 13 according to a predetermined code algorithm, and then sent from the interface LSI unit 12 to the transmission line. be done. Note that the reverse process is performed for decoding. Further, APCi, APCout represent input and output of adaptive predictive coding signals, respectively.

Here, the interface circuit of the present invention is used to interface the digital signal calculation unit 13 and the PCM-C0D [IC#, and converts input parallel data into serial data and outputs it. , or write the next frame of data after reading,
Alternatively, it is required that there is sufficient time before reading starts.

Note that the interface circuit must store data from one frame before, but it is necessary to improve data transfer efficiency.

[Conventional technology]

Figure 5 is a block diagram of the conventional example, Figure 5 (al is a block diagram of the interface circuit, Figure 5 (b) is the block diagram of the interface circuit,
FIG. 6 shows a block diagram of the control circuit in FIG. 1, and FIG. 6 is an explanatory diagram of the operation of FIG. The operation shown in FIG. 5 will be explained below with reference to FIG.

First, an external system clock and a load signal are applied to the AND gate 21 in FIG. 5 (bl), and only when the latter is 1, the system clock becomes the write clock (
(hereinafter abbreviated as W-CK) from the AND gate 21 to the # register 15 in FIG. 5(a).

Therefore, the parallel data manually input from the internal bus is written to the #registor (see Figure 6 - ■, ■, ■).

Next, the input synchronization signal shown in FIG. Since it is added to the set terminal of , 1 is output from this and the AND gate 27 is turned on. Therefore, the read clock (hereinafter abbreviated as R-CK) shown in FIG.
8 and is added to the counter 29.

Here, the selector 28 changes the a side to 0 when the synchronization signal is 1.
Since the b side is selected when , the system clock is output from the selector 28 only while the synchronization signal is 1, as shown in ◯ and ◯ in Fig. 6.

In addition, the counter 29, which is reset using the synchronization signal as described above, counts the input R-GK from the initial value, and when it counts 1, for example, 4, it sends out an MSB (most significant digit) signal and stops operating. However, the changing point of this MSB signal is detected by the differentiating circuit 22°, and the inverted signal is applied to the reset terminal by the inverter 25 to restore the latch 26 and the AN
Because D gate 27 is turned off.

As shown in Figure 6-○, 4-bit R-CK is selected by selector 8.
is output from.

Now, the first bit of the parallel data transferred from the #registor 15 and stored in the #2 register 16 shown in FIG. 5 (is) is read out by the system clock shown in FIG. is read using R-C. Note that when the data stored in #2 register j6 is read out one after another and this register becomes empty, the MSB signal is sent from the counter 29, so the inverter 2
Data transfer from register #1 to register #2 is performed using Homare-C generated using the output of register #5.

[Problem to be solved by the invention]

Here, the data transfer from the # register 15 to the #2 register 16 is from the counter 29 as described above. Since this is performed when the ISB signal is sent out, there is a problem in that when the #2 register 16 is empty, data transfer is delayed and data transfer efficiency is reduced.

The present invention aims to improve data transfer efficiency.

[Means to solve problems]

FIG. 1 shows a block diagram of the principle of the present invention.

In the figure, 5 is a #clock generation means that generates a clock for the #1 register using a load signal and a system clock, and 6 is a storage of the input load signal, a read end signal from the #2 clock generation means, and I2 data. #l indicates the data storage state of the #1 register using the status flag
This is a #1 data storage state flag generating means that generates a data storage state flag.

Further, 7 is an I2 data storage state flag generating means for generating an I2 data storage state flag indicating the data storage state of the #2 register by using the load signal, the read end signal, and the #data storage state flag; Using the synchronization signal, the read clock, the system clock and the l12 data storage status flag.

When the #2 register is empty, the parallel data written to the #2 register is immediately transferred to the #2 register.

This is #2 clock generation means that generates a clock for #2 register for reading out serial data.

[Effect]

The present invention includes #data storage state flag generating means 6 which generates a flag indicating the data storage state of the #registor in #l register 1, and II2 data which generates a flag indicating the data storage state of the 12 registers in 12 register 2. A storage state flag generating means 7 is provided respectively.

Then, when the I2 data storage state flag generating means 7 is O indicating that the #2 register 2 is empty.

When data is loaded into #l register 1, it is simultaneously transferred to #2 register.

As a result, data is immediately read out in series from the 12 registers 2 and output, thereby improving data transfer efficiency.

〔Example〕

FIG. 2 is a block diagram of the embodiment, and FIG. 3 is an explanatory diagram of the operation of FIG. 2. Note that the symbols on the left side of FIG. 3 indicate the waveforms of the portions with the same symbols in FIG.

Here, inverter 51. NAND gate 52 is #1
A component of the clock generation means 5, an inverter 61. #
1 flag register 62 is a component of #1 data storage status flag generating means 6, and is an AND gate? 1.72. Flip-flop73. OR gate? 4.75. The inverter 76 and the #2 flag register 77 are the components of the I2 data storage status flag generating means 7, and the ND gate 81.8
1°, differential circuit 82.82", inverter 83.83'
, latch 84. Flip-flop 84', OR
Gate 85. Selector 86° counter 87. Rise detector 88. A fall detector 89 represents a component of the #2 clock generating means 8. The operation shown in FIG. 3 will be explained below with reference to FIG.

First, in the initial state, the #register and #2 register are empty, so the outputs of the #flag register 62, 12 and flag register 77, which indicate the status of these registers, are shown on the left side of ○ and ■ in Figure 3. As shown, the AND gate 71 becomes O and 1 is added via the inverter 76, and the AND gate 71 is in the on state.

Now, when a load signal as shown in FIG. flip-flop (hereinafter referred to as
(abbreviated as FF)73. #2 via OR gate 75
They are added to the set terminals of the flag register 77, respectively.

Therefore, the ++i flag register 62 is set to 1 in the next cycle.
outputs and holds that state until a reset is input. Further, the #2 flag register 77 outputs 1 one cycle later than the #flag register 62 due to the FP 73, but the output of 1 from the FF 73 is added to the reset terminal of the #flag register 62 via the OR gate 74. This register is reset (Figure 3-■).

(See the middle part of ■).

Here, the AND gate 81 is turned on by the 1 from the #2 flag register 77, so the input synchronization signal passes through this gate and is differentiated by the differentiating circuit 82, then inverted by the inverter 83, and the latch 84 input to the set terminal. Therefore, 1 is output from this latch, but this output l is input to the AND gate 81' via the OR gate 85, so this gate is turned on and the clock CK
passes through this gate 81' to counter 87 and selector 8.
Enter 6.

Therefore, when the counter 87 starts counting operation and counts only the predetermined data length, l MSB
The (top) signal is sent to the differentiating circuit 82', which differentiates the MSB signal and sends the differential output to the reset terminal of the latch 84 via the inverter 83' and directly to the FP5.
84', the latch 84 is reset and outputs 0.

On the other hand, since the FF 84' sends out the inverted differential output delayed by 1 bit to the AND gate 81'' via the OR gate 85, the clock CK with 1 bit extra than the data length counted by the counter 87 is sent to the selector 86. This is to ensure that the first bit of data does not lag behind the synchronization signal by ensuring that the first bit of data is output before the next reading starts from the l12 register (not shown). .

Next, as the clock for the #1 register, the load signal and the system clock are NANDed by the NAND gate 52.
The clock shown in Figure 3-0 is used as the register clock, and as mentioned above, when the load signal is input when the output of the #2 flag register 77 is 0, the output of l is delayed by one cycle from the FF 73. is sent out and added to the selector 86 as a selector control signal, so the selector 86 selects the system clock SCK (the third
When the control signal is 0, the clock (J is selected and output as the clock for the s2 register (the CK part on the right side of Figure 3)).

Therefore, the I12 register takes in the data written in the Il register using the 1-bit system clock SCK shown in FIG. 3-0, converts it into serial data using the clock on the right side of FIG. 3-0, and outputs the data.

Note that one register in the #l register becomes empty as shown in the middle of the circle in Figure 3, but another data is written at the rising edge in the middle of the circle in Figure 3, and the output of the l# flag register becomes 1.

Now, the rising edge of the output of FF84' is detected by the rising edge detector 88.
When the falling edge is detected, the #1 flag register 62 and the #2 flag register 77 are reset, and the falling edge is detected by the falling edge detector 89.
When detected, #2 flag register 77 is set.

Then, when the I2 register finishes outputting SR, PP8
The data in the #l register is transferred to the I2 register by the MSB of the counter 87 through 4'.

That is, flags are provided in the #l register and the I2 register, respectively, to indicate whether or not there is unprocessed data.

When the I2 register is empty, data is loaded into the It register and can be transferred to the 12 register at the same time, improving data transfer efficiency.

〔Effect of the invention〕

As described above in detail, according to the present invention, the effect of improving data transfer efficiency can be obtained.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram of an embodiment of the invention, Fig. 3 is an explanatory diagram of the operation of Fig. 2, Fig. 4 is a configuration diagram of a high-efficiency GODEC, and Fig. 5 is a block diagram of an embodiment of the present invention. A block diagram of the conventional example, FIG. 6 shows an explanatory diagram of the operation of FIG. 5. 1 is the #1 register, 2 is the 12 register, 5 is the #clock generation means, 6 is the #1 data storage state flag generation means, and 7 is! 12 indicates data storage state flag generating means, and 8 indicates #2 clock generating means. The width of the 1-bed sheet of the book's opening... Figure 1 Concave high riser C0DEC Yokonaga Figure 4
67 (a) A>'fl71x-';A[=;1'21
) 7'O Noah ER-C (b) 5 concave [α) trfσ notice・[I wholesale reversal flow・/
qei L East Illi no Flow 77 Figure $ 5 Figure

Claims (1)

[Claims] Parallel data input via the line is stored in the #1 register (1).
#1 clock generation means (5) that generates a clock for the #1 register using the load signal and the system clock in the interface circuit that writes data to the #2 register (2) and outputs it as serial data. , Generates a #1 data storage state flag indicating the data storage state of the #1 register using the input load signal, the read end signal from the #2 clock generating means (8), and the #2 data storage state flag. A #1 data storage state flag generating means (6) generates a #2 data storage state flag indicating the data storage state of the #2 register using the load signal, the read end signal, and the #1 data storage state flag. Using the #2 data storage state flag generating means (7), the synchronization signal, the read clock, the system clock, and the #2 data storage state flag, when the #2 register is empty, the #2 data storage state flag is written to the #1 register. An interface circuit comprising: #2 clock generating means (8) for generating a #2 register clock for immediately transferring parallel data to the #2 register and reading out serial data.