JPH01268338A - Psk demodulating circuit - Google Patents

Abstract

PURPOSE:To obtain a circuit which is independent of a carrier frequency of an input signal and a data speed by detecting directly a phase variation point from a coherent two-phase PSK modulation input signal by only a comparator. CONSTITUTION:A comparator 2 compares a coherent two-phase PSK input signal 1 with a reference voltage V1 and outputs a demodulation carrier wave square signal 3, and a comparator 6 compares a full-wave rectifying signal 5 by a full-wave rectifying circuit 4 with a reference voltage V2 (V2>V1) and outputs a demodulation clock signal 7. A flip-flop 8a outputs a carrier wave square signal 9 synchronizing with a clock signal, and a flip-flop 8b outputs a demodulation carrier wave square signal 10 which has been delayed by on clock. An exclusive NOR circuit 11 outputs a phase variation point detecting signal 12, and outputs a demodulating signal 15 through flip-flops 8c, 8d. In such a way, the circuit which does not depend a carrier wave frequency of the coherent two-phase PSK modulating signal and the data speed can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a PSK demodulation circuit that demodulates a coherent two-phase PSK modulated signal.

[Conventional technology]

Conventionally, this type of circuit has been shown in FIG. Third
In the figure, (1) is a coherent two-phase PSK signal, (to) is a double multiplier, αη is a low-pass filter with a data band, (to) is a phase comparator, and (1) is a data signal.・Low pass filter for band, (1) regenerates the clock signal vCO1@ has a band that passes the carrier frequency twice that of (1).・Pass filter.

(c) is a VaO that reproduces twice the carrier signal of (1),
(F) is a branching unit, (E) is a phase adjuster, and (E) is a phase detector.

@Ha Converter, @td, D type flip-flop, Q5 is demodulation signal.

Next, the operation will be explained. In the yg3 diagram, the coherent two-phase P8Ki input signal (1) is
Multiply by fe. The signal multiplied by 2 is separated by two filters (7) and (2).

The signal passed through the low pass filter (7) having a data band is passed through a nine phase comparator (1sa) and a band pass filter having a data band. A clock signal is regenerated from a coherent two-phase PSK modulated input signal (1) by a PLL composed of Om. On the other hand, the signal that has passed through a band pass filter (which has a band that passes a carrier frequency twice that of the input signal) is passed through one phase comparator (
1sh) and loop band filter 4 and CO (c)
This signal is divided by μ by a frequency divider (C) by 9, and is converted into a coherent 2-phase P8K modulated input signal (1) by a PLL consisting of A 0 degree carrier wave having the same frequency as the human signal (11) is regenerated.The regenerated 0 degree carrier wave is converted into a coherent 2-phase PA
After synchronizing with the t<'z-adjusted input signal 1), the phase is compared with the human input signal (1) using a 1-phase detector (e). Since the output of phase comparator 4 is almost equal to the demodulated signal, it is still an analog signal.

Convert to square wave using comparator @. The output of the comparator (2) is input to the data input terminal of the iJ type flip-flop (c). The clock input terminal of the D-type flip-flop (to) is supplied with the clock reproduction signal obtained from the output of VaO (1) through a phase adjuster (25a).
, a clock signal synchronized with the coherent two-phase PSK modulation input signal (11) is input. Therefore, the output of the D-type flip-flop is the coherent two-phase PSK modulation input signal (11).
A demodulated signal O5 synchronized with the modulated input signal (1) is obtained.

[Problem to be solved by the invention]

As described above, the conventional PSK demodulation circuit uses four filters and two COs to perform coherent two-phase PSK
Since it has a carrier wave recovery circuit and a clock recovery circuit adapted to the modulated input signal, the circuit constants must be reset each time the carrier wave frequency and data rate of the input signal change.

In addition, it is necessary to readjust the two phase fA adjustment circuits each time.9 Furthermore, since the constituent circuits are analog circuits that are affected by temperature, there are problems such as poor temperature characteristics.

This invention was made to solve the above problems, and is independent of the carrier frequency and data rate of a coherent two-phase PSK modulated input signal, that is, any coherent two-phase PSK modulated signal can be demodulated without adjustment. Along with this, PSK operates stably against temperature changes.
The purpose is to obtain a demodulation circuit.

[Means to solve the problem]

The PSK demodulation circuit according to the present invention has a coherent two-phase PSK demodulation circuit.
By removing the circuit configuration having a carrier wave recovery circuit and a clock recovery circuit that are compatible with the carrier wave frequency and data rate Jν of the 8K i-tone signal, a coherent two-phase PSK'fl! In addition to using a circuit configuration that uses a comparator to detect the phase change point from the signal itself.

[Operation] The PSK demodulation circuit in this invention is a 5 coherent 2
By directly detecting the phase change point from the phase PSK modulated signal, the circuit can be made independent of the carrier frequency and data rate of the coherent two-phase PSK modulated signal, and the circuit that is affected by temperature due to digital circuitization can be eliminated. This makes it possible to obtain stable characteristics against temperature changes.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, (1) is a coherent two-phase PSK modulation input signal, (2) is a comparator, (3) is a demodulated carrier wave rectangular signal output by (2), (4) is a metal plate rectifier circuit, (5)
(4) is a full-wave forward current signal outputted, (6) is a comparator with a different comparison voltage from (2), (7) is a demodulated clock signal outputted by (6), and (8) is a D-type clip. The flop, (9) is a demodulated carrier wave rectangular signal synchronized with the demodulated clock signal by (8a), and the signal is 1 from (9) by (8b).
Carrier wave rectangular signal delayed by a clock.

(6) is an Exiclusop Noah circuit, ■ is a phase change point detection signal with an output of 0, a3 is an invert circuit that inverts the phase of (7), and (b) is a Gino Zard signal removed by (8C). The phase shift detection signal (to) is the demodulation signal.

In FIG. 1, a coherent two-phase P8Ki input signal (1) is simultaneously input to a comparator (!) and a full-wave rectifier circuit (4).

Comparator (2) fi + coherent 2-phase PS
The K input signal (1) is compared with the base pressure v1, and a demodulated carrier wave rectangular signal (3) shown in FIG. 2(c) is output. On the other hand, the full-wave rectifier circuit (4) receives the coherent two-phase PSK input signal (
1) is input, full-wave rectification is performed, and a full-wave rectified signal (5) shown in FIG. 2(d) is output. The comparator (6) converts the full-wave rectified signal (5) into the fundamental voltage V!V! >vt ) and outputs a demodulated clock signal (7) shown in FIG. 2(c).

The flip-flop (8a) receives the demodulated carrier rectangular signal (
3) using the demodulated clock signal (7) 1 Figure 2 (f)
A nine-carrier rectangular signal (9) is output in synchronization with the clock signal shown in FIG. This carrier wave rectangular signal (9) is outputted by a flip-flop (to) as a demodulated carrier wave rectangular signal α9 delayed by l clocks from the clock period demodulated carrier wave rectangular signal (9) as shown in FIG. 2(g).

The FC-flusive NOR circuit 0 inputs the demodulated carrier rectangular signal (9) synchronized with the demodulated clock signal and the demodulated carrier rectangular signal GO delayed by 1 clock (9).
The phase change point detection signal υ shown in (h) is output. This signal @ contains the /Szard signal because the F/F NOR circuit is asynchronous.

The phase change point detection signal (to) containing the hazard signal is a clock signal obtained by inverting the phase of the demodulated clock signal (7) by 180 degrees by the inverter circuit 03, and is re-checked by the flip-flop (8c). As shown in FIG. 2(i), the signal is shaped into a phase change point detection signal (to) from which the hazard signal has been removed.

Phase change point detection signal QJd from which the hazard signal has been removed,
The flip-flop (8d) outputs a demodulated signal 4 as shown in FIG. 2(j).

In the above embodiment, the flip-flop (8) is D
Although a type flip-flop is shown, a flip-flop may be used for J-, and the same effect as in the above embodiment can be obtained.

〔Effect of the invention〕

As described above, according to the present invention, since the phase change point is directly detected from the coherent two-phase P8Kiv4 human signal using only the comparator, general-purpose PSK demodulation that does not depend on the carrier frequency or data rate of the input signal Digitalization has the effect of providing stable operation against temperature changes.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the PSK demodulation circuit according to the present invention, FIG. 2 is a diagram showing the operation of the PSK demodulation circuit according to the invention, and FIG. 3 is a diagram showing a conventional PSK demodulation circuit. In the figure, (1) is a cohesive reflex) two-phase PSK variable % input signal, (2) is a comparator, (3) is a demodulated carrier wave rectangular signal, (4) is a full-wave [flow circuit], and (5) is a full-wave rectified signal. ,
(6) is a comparator, and (7) is a demodulated clock signal. (8) is a D-type flip-flop; (9) is a demodulated carrier rectangular signal synchronized with the demodulated clock signal;
NOR circuit, (2) is the phase change point detection signal, Q3 is the inverter circuit, 041 is the phase change point detection signal from which the hazard signal has been removed, 05 is the demodulation signal, Ql is the double multiplier, αη
is a low pass filter with a data band, aS is a phase comparator, (to) a low pass filter for the hatter band p, eA is a VCO for clock signal regeneration, @ is (1
) is a band pass filter that passes twice the frequency of (1), @ is a loop band filter, @ is a VCO that reproduces a carrier frequency twice that of (1), (2) is a frequency divider,
) is a phase adjuster, (e) is a phase detector, @ is a comparator, and @ is a D-type flip-flop. Note that the same or corresponding parts in FIG. 1 are designated by the same reference numerals.

Claims (1)

[Claims] A first comparator inputs a coherent two-phase PSK signal and converts the input signal into a rectangular wave; a full-wave rectifier circuit demodulates a clock signal from the input signal; a second comparator; A first flip-flop that reads the output of the comparator, a second flip-flop that delays the output of the first flip-flop by one clock, and a first flip-flop output and a second flip-flop output. Comparing the exclusive Noah gate circuit and the exclusive Noah gate circuit
The third step is to remove the hazard signal from the waveform of the gate circuit output.
A PSK demodulation circuit comprising: a flip-flop; and a fourth flip-flop which inputs the third flip-flop and demodulates a PCM signal.