JPH02279050A - Psk demodulation circuit - Google Patents

Abstract

PURPOSE:To able to demodulate any coherent biphase PSK modulation signal with no adjustment and to attain stable operation against temperature change by using a comparator and a shift register so as to apply digital correlation to the coherent biphase PSK input signal, and detecting a phase change point. CONSTITUTION:A circuit comprising a carrier reproducing circuit and a clock reproducing circuit in matching with the carrier frequency and data speed of a coherent biphase PSK modulation signal 1 is omitted and 4-bit correlation is taken from the coherent biphase PSK modulation signal 1 with a comparator 6 and a shift register 8. Thus, the circuit constitution detecting a phase change point is adopted in this way and a digital circuit is used in place of an analog circuit. That is, a phase change point is directly detected by the coherent biphase PSK modulation signal 1. Thus, the circuit independently of the carrier frequency and the data speed of the coherent biphase PSK modulation signal 1 is obtained. Moreover, stable characteristic against the temperature change is obtained through digital circuit configuration.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a psx demodulation circuit that demodulates a coherent two-phase PaK modulated signal. There was something shown. Third
In the figure, (1) is a coherent two-phase PBK modulation input signal, αa is a 2x multiplier, aη is a low pass filter with a data band, 6g is a phase comparison i, and a9 is for the data band. (2) is a low pass filter that has a loop bandwidth.・VC that regenerates twice the carrier signal of the filter, Noke+11
o, r24 are frequency dividers, (c) is a phase adjuster, 0 is a phase detector, @ is a comparator (to) is a D-type flip-flop, tts is a demodulation signal O Next, we will explain the operation b do. In Figure 3.

The coherent two-phase PSK modulated input signal (1) is
Multiply the amount by 2 using the multiplier ae. The signal that is 2 times higher is
With two filter fins. Divided by υ. The signal that has passed through the low pass filter αηta having a data band is input to a coherent two-phase PSK modulation by a PLL consisting of a single phase comparator (18a), a band pass filter α having a data band and a VCO. Regenerate a clock signal from signal (1).

On the other hand, a band pass filter C! has a band that allows a carrier wave frequency twice that of the input signal to pass through. The signal that has passed through υ is processed into a coherent 2
In phase P9, a 0 degree carrier wave twice the carrier wave is reproduced from the modulated input signal +11.

This signal is divided into 1/2 by a divider @.

The coherent 2-phase PSK modulation input signal (0 degree carrier wave having the same frequency as 11 is regenerated. The 0 degree carrier wave that is regenerated is transmitted to the 0 phase adjuster (251)), and the coherent 2 phase PSK modulation input signal
After synchronizing with the phase psx modulation input signal (11), the phase is compared with the input signal (1) using the phase detector (1).The output of the phase comparator (c) is almost equal to the demodulation signal, but still Since it is an analog signal, a comparator is required) to convert it to a square wave. The output of the comparator @ is input to the data input terminal of the D-type flip-flop □□□. The clock input terminal of the D-type 7 lip-flop (to) is connected to vcog.
The clock reproduction signal obtained from the output of B is passed through a phase adjuster (
2Sa) Yoshi.

A clock signal synchronized with the coherent two-phase psx modulation input signal +11 is input. Therefore, the output of the D-type flip 70 tube is a demodulated signal α synchronized with the coherent two-phase PSK modulated input signal (11).

[Problem to be solved by the invention]

As described above, the conventional PSK demodulation circuit uses four filters and two vCOs, and supports coherent two-phase PSK.
Since it has a carrier recovery circuit and a clock recovery circuit that are compatible with the modulated input signal, the circuit constants must be reset each time the carrier frequency and data rate of the input signal change, and the two phase adjustment circuits also need to be reset. It required readjustment each time, and furthermore, since the component circuits were analog circuits that were affected by temperature, there were other problems such as poor temperature characteristics.

This invention was made to solve the above-mentioned problems, and is independent of the carrier frequency and data rate of a coherent two-phase PSK modulated input signal, that is, any coherent two-phase PSK modulated signal can be demodulated without adjustment. , psx that operates stably against temperature changes
The purpose is to obtain a uI tuning circuit.

[Means to solve the problem]

The PSK demodulation circuit according to the present invention has a coherent two-phase p
A circuit having a carrier wave recovery circuit and a clock recovery circuit that match the carrier frequency and data rate of the sx modulated signal is removed, and the phase change point is determined by correlating the coherent two-phase PSK modulated signal with 4 bits using a comparator and a shift register. In addition to the circuit configuration for detection, the analog circuit is replaced with a digital circuit.

[Effect]

The psK demodulation circuit in this invention can be made into a circuit that does not depend on the carrier frequency and data rate of the coherent two-phase PSK modulation signal by directly detecting the phase change point of the coherent two-phase PSK modulation signal, In addition, by eliminating the need for circuits that are affected by temperature changes due to digital circuitry, stable characteristics can be obtained against multiple temperature changes.

〔Example〕

An embodiment of the present invention will be discussed below with reference to the drawings. 1st
In the figure, (1) is a coherent) two-phase PSK modulated input signal, (2) is a comparator, (3) is a demodulated carrier wave rectangular signal outputted by (21), and (4) is a full-wave rectifier circuit.

(5) is the full-wave rectified signal output by (4), and (C) is the (2
1 and a comparator with a different comparison voltage, (7I is (61
The demodulated clock signal j (8) output by is a 4-bit shift register, (9) is a 4-bit parallel signal output by (8), aO is a decoder that decodes the input BOD signal into a decimal signal, +111 is a phase shift detection signal 1. which indicates a phase shift of the input signal (1) at an output. (13 is the phase shift detection signal 2 which is the output of αυ and indicates the phase shift of the input signal +11. IJ3 is an inverter circuit, (14 is a flip-flop at J- which inputs the H output signal, and α9 is a demodulation signal.

In Figure 1, the coherent two-phase PSK modulation input signal +11 is connected to the comparator (2) and the full-wave rectifier circuit (4).
input at the same time. A comparator (2) compares the coherent two-phase PSK modulated input signal 0) with a reference voltage v1 and outputs a demodulated carrier wave rectangular signal (3) shown in FIG. 2(C).

On the other hand, the full-wave rectifier circuit (4) inputs a coherent two-phase psK modulated input signal (11) and performs full-wave rectification as shown in Figure 2(d).
The full-wave rectified signal (5) shown in The comparator (6) is.

The full-wave rectified signal (5) is converted to the reference voltage V2 (V2 )Vl)
A demodulated clock signal ( ) shown in FIG.

The 4-bit shift register (8) reads and shifts the demodulated carrier wave rectangular signal (3) using the demodulated clock signal (7). Output signal of 4-bit shift register (8) (
9) The value of 4 bits is expressed in Hgx (hexadecimal) as shown in Fig. 2(f).
When there is one phase shift repeatedly, Bagx・6HExsD
, and 'HEX' HIX #2HRX
Continuously outputs 11X.

The decoder α inputs the output signal (91) of the 4-bit shift register (8) and decodes it into a decimal number.

Phase change detection signal 1 (Il
l.

At the time of BHRX, a phase change detection signal 2α2 is output.

The phase change detection signal 1α11 and the phase detection signal 2° are
J- is input to the K and J terminals of the flip-flop, respectively. Flip to J-, 70 knobs (clock)
When the demodulated clock signal (71) is inputted to the g#A child driver and the NIO degree phase inversion signal is input to the inverter circuit a3, the J-
The flip-flop outputs the demodulated signal α shown in FIG. 2(1).

In the above embodiment, 'M' is used as the decoder eel output signal.
I used ``1'' and ``MIX,'' but you can also use ``m'' HHX and BHRX or DH, x and 2□8.

In addition, the flip-flop α4 is set/reset/
You can also use flip-flops (the same effect as in the above example will be achieved).

〔Effect of the invention〕

As described above, according to the present invention, since the comparator and the shift register are configured to digitally correlate the coherent two-phase PSK human signal to detect one phase change point, the carrier wave frequency of the input signal is A general-purpose PSK demodulation circuit that does not depend on data speed or data rate has been created, and has the effect of providing stable operation against temperature changes (due to digitalization).

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of the PSK demodulation circuit according to the present invention, FIG. 2 is a diagram showing the operation of the PSK demodulation circuit according to the invention, and FIG. 3 is a diagram showing a conventional PSK demodulation circuit. In the figure, (1) is a coherent two-phase PSK modulated input signal, (2) is a comparator, (3) is a demodulated carrier wave rectangular signal, (4) is a full-wave rectifier circuit, and (5) is a full-wave rectified signal. (6) is a comparator, (7I is a demodulation clock, (8)
is a 4-bit shift register, +91tj: shift register
The parallel output signal of the register, a. is a decoder that decodes BCD into a decimal number, and the convergence is the phase shift detection signal 1. H is the phase shift detection signal 2.0 is the inverter circuit, (I4 is J
- is a flip-flop, a9 is the demodulated signal, ae is the second position, αη is the low pass filter with the data band, as is the phase comparator, al is the low pass filter for the data band, and co is the low pass filter for the data band. Clock (VOO for playback)
, clυ is a band that passes twice the frequency of (11).
Pass filter, (2) is a loop filter, (to) is a VCo that reproduces twice the carrier frequency of (!:), @ is a divider, @ is a phase adjuster, ■ is a phase detection!, Cut=r
The comparator @ is a D-type flip-flop. Note that the same or corresponding parts in FIG. 1 are indicated by the same reference numerals.

Claims (1)

[Claims] A first comparator inputs a coherent two-phase PSK signal and converts the input signal into a rectangular wave; a full-wave rectifier circuit demodulates a clock signal from the input signal; a second comparator; A 4-bit shift register that is read using the comparator output, and a BCD (Binary Coded) of the 4-bit shift register.
A PSK demodulation circuit comprising: a decoder that inputs an output signal (Decimal) and converts it into a decimal number; and a flip-flop that inputs the output of the decoder and demodulates a PCM signal.