JPH01269143A - Storing buffer control system - Google Patents

Abstract

PURPOSE:To evade the processing delay of a storing command registered in a storing buffer and to improve the performance of an arithmetic processing without delaying the processing of a reading request to a cache memory by indexing the address of the storing command stored into the storing buffer independently from the index at an address array. CONSTITUTION:Independently from an index at an address array 6 to hold the address of data stored into a cache memory for an instruction, the address of the storing command stored in a storing buffer 7 by an address holding means 5 to hold the same contents as the address array 6 is indexed. In accordance with the index result, the processing of the storing command to a cache memory for an instruction and operand is executed. Thus, without delaying the processing of the reading request to the cache memory, the processing delaying of the storing command registered at the storing buffer can be evaded and the performance of the arithmetic processing can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a store buffer control system, and more particularly to a cache memory indexing system for store commands in an arithmetic processing unit having two cache memories, one for instructions and one for operands.

Conventionally, in an arithmetic processing unit that has a cache memory and uses a pipeline method, the address calculation for a store command is performed before the instruction is executed, and the store data for the store command is obtained after the instruction is executed. , store data is not required at the time of cache memory indexing for a store command.

Therefore, if the cache memory is indexed after the store data is obtained, that is, after the store command address and data are available, the cache memory can be accessed in one go.

For this reason, the arithmetic processing unit is provided with a store buffer, a store address is registered in this store buffer, it waits for the store data corresponding to the store command to be requested, and when the store data is requested, the store address is By registering in the store buffer, the address and data to be stored in the cache memory are aligned.

When the address and data are in the store buffer,
An index request is made to the cache memory, and when this index request is accepted by the cache memory, the cache memory is indexed. As a result of indexing the cache memory, if the corresponding address is registered, the store data registered in the store buffer is written to the cache memory.

If there are two cache memories, one for instructions and one for operands, an index request will be issued to each of the two cache memories.

In a cache memory, read requests are usually processed with priority over store requests, so the processing speed of a cache memory index request based on a store command varies depending on the frequency of read requests to the cache memory. The frequency of this read request increases as the amount of prefetched data for instructions and operands increases.In particular, the amount of prefetched data in the instruction cache memory is large, so the processing of an index request by a store command for this instruction cache memory takes a long time. You will have to wait.

In such conventional arithmetic processing units, read requests to the cache memory are processed with priority over index requests to the cache memory by store commands registered in the store buffer. If the number increases, an index request to the cache memory by a store command will have to wait for a long time, resulting in a delay in the processing of the store command.

Additionally, if the index request of the store commands to the cache memory is kept waiting for a long time, the store buffer will accumulate more store commands than its capacity, so it is necessary to stop the calculation process and process the store commands registered in the store buffer. This has the disadvantage that the performance of arithmetic processing decreases.

The present invention was made in order to eliminate the drawbacks of the conventional methods as described above, and it is possible to reduce the processing delay of store commands registered in the store buffer without delaying the processing of read requests to the cache memory. It is an object of the present invention to provide a store buffer control method that can avoid this problem and improve the performance of arithmetic processing.

The store buffer control method according to the present invention includes a cache memory for instructions and operands, an address array that holds addresses of data stored in the cache memory for instructions, and a method for writing data to the cache memory. A store buffer control method for an arithmetic processing unit having a store buffer for storing a store command to be loaded, wherein the address holding means holds the same contents as the address array, and the index in the address array is independently stored. indexing means for indexing the address of the store command stored in the store buffer by the address holding means, and processing of the store command with respect to the cache memory is performed according to the index result of the indexing means. Features.

1MヱNext, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In FIG.
4, instruction address arrays (SIAA and IAA) 5, 6, a store buffer 7, and a control circuit 8.

The operand address array 4 stores block addresses of data registered in an operand cache memory (not shown).

The instruction address array (SIAA) 5 includes an instruction address array (SIAA) in which block addresses of data registered in an instruction cache memory (not shown) are stored.
The contents of IAA) 6 have been copied.

The operand read address is input to the operand address array 4 via the operand address signal line 100 and the selector 1, and index processing of the operand address array 4 is performed using this address, and data is registered in the operand cache memory. It is determined whether the

Further, the operand store address is registered in the store buffer 7 via the operand address signal line 100,
The user is made to wait until the store data is obtained in the store buffer 7.

The instruction read address is input to the instruction address array 6 via the instruction address signal line 101 and the selector 3, and index processing of the instruction address array 6 is performed using this address, and data is registered in the instruction cache memory. It is determined whether the

The instruction address array 5 has an instruction address signal line 101.
An instruction address is inputted via the selector 2 and the instruction address array 6, and the same contents are written when the instruction address array 6 is written, so that the same contents as the instruction address array 6 are guaranteed.

The store command in the store buffer where the store data was requested is the store address signal 11102 and the selector 2.
The store address is output to the instruction address array 5 via the store address signal line 102 and the selector 1, and the store address is output to the operand address array 4 via the store address signal line 102 and the selector 1.
Output to. Using this address, the operand address array 4 and the instruction address array 5 are indexed.

The selector 2 uses the store address signal! except when updating the contents of the instruction address arrays 5 and 6. 1102, the indexing of the instruction address array 5 using the store address, that is, the indexing of the instruction cache memory, is performed with almost no waiting, and the index result is used for control. line 10
3 to the control circuit 8.

In addition, since the selector 1 normally selects the operand read address that is input via the operand address signal line 100, indexing of the operand address array 4 using the store address cannot be performed until the operand read address stops. However, since operand reading does not involve as many pre-fetching operations as instruction reading does, that is, it is used less frequently, indexing of the operand address array 4 using a store address does not have to wait for a long time.

The control circuit 8 determines that the index result of the instruction address array 5 based on the store address input via the control 1i103 is
When indicating that the data corresponding to this store address is not registered in the instruction cache memory, the operand address array 4 according to this store address
Waiting for the completion of the indexing process of the cache memory for operands, control is performed via the control line 106 to proceed to processing of the next store command registered in the store buffer 7.

When the index result of the instruction address array 5 based on the store address input via the control line 103 indicates that data corresponding to this store address is registered in the instruction cache memory, the control circuit 8 The control lines 104 and 10 instruct the cache memory for instructions and the cache memory for instructions to give the store address a higher priority than the address of the read request.
5, selector 1.3 selector stores address signal line 102
Controls the selection of the store address input via the . This causes the store address to be processed.

In other words, if the data corresponding to the store address is not registered in the instruction cache memory, the store command is processed without stopping the processing of the instruction read request, and the data corresponding to the store address is registered in the instruction cache memory. If there is a store command, the control circuit 8 is controlled to process the store command preferentially.

In this way, in order to independently index the instruction cache memory using the store address of the store command registered in the store buffer 7, the block address of data registered in the instruction cache memory is stored. An instruction address array 5 is provided that holds the same contents as the instruction address array 6 that is stored in the instruction address array 6, and the instruction address array 5 is provided with an instruction address array 5 that holds the same contents as the instruction address array 6. By processing the store command, it is possible to avoid a delay in processing the store command registered in the store buffer 7 without delaying the processing of the read request to the cache memory.

That is, by using the instruction address array 5 to index the instruction cache memory using the store address, it is possible to process the store command without stopping the processing of the read request, and the data corresponding to the store address is Even if the command is registered in the instruction cache memory, the store command can be processed with priority over the read request, so there will be no delay in the processing of the store command.

In addition, index requests to the cache memory by store commands will not have to wait for a long time, and store commands that exceed the capacity will not accumulate in the store buffer 7, so arithmetic processing will be stopped and store commands registered in the store buffer will be processed. There's no need to do that. Therefore, according to the present invention, it is possible to improve the performance of arithmetic processing.As explained above, according to the present invention, the address of the data stored in the instruction cache memory is independent of the index in the address array that holds the address of the data stored in the instruction cache memory. Then, the address of the store command stored in the store buffer is indexed by an address holding means that holds the same contents as this address array, and the store command is processed for the instruction and operand cache memories according to the index result. By doing this, it is possible to avoid delays in the processing of store commands registered in the store buffer without delaying the processing of read requests to the cache memory, and it is possible to improve the performance of arithmetic processing. effective.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. Explanation of symbols of main parts 1 to 3...Selector 4...Address array for operand 5.6...
...Instruction address array 7...Store buffer 8...Control circuit

Claims (1)

[Claims] (1) It has a cache memory for instructions and operands, an address array that holds addresses of data stored in the cache memory for instructions, and a store buffer that stores a store command to be written to the cache memory. A store buffer control method for an arithmetic processing unit, wherein the address holding means holds the same contents as the address array, and the address of the store command stored in the store buffer is stored independently of an index in the address array. 2. A store buffer control system, comprising: indexing means for indexing by said address holding means, and processing of said store command for said cache memory is performed in accordance with an index result of said indexing means.