JPH01278043A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable the stable Al pillar method with superior reproducibility by forming a lower wiring of copper, sticking an Al layer thereon, forming a resist pattern turning to a mask for pillar, performing reactive ion etching of the Al layer via the resist, and forming a pillar. CONSTITUTION:A copper layer 1 is formed by sticking copper on a substratum insulating layer 9, an Al layer 2 is formed by sticking aluminum thereon, photo resist is spread, and patterned resist 5 is formed by exposure through a mask for pillar, and by development. The Al layer is etched by reactive ion etching using the resist 5 as a mask, thereby forming a pillar 2, and then the resist 5 is eliminated. Photo resist is again spread, exposure is performed through a mask for lower layer wiring, and a patterned resist 6 is formed by development. By using the resist 6 as a mask, the copper layer is patterned, and a lower layer wiring 1 is formed. Thereby an aluminum pillar method can be stably executed with superior reproducibility.

Description

[Detailed Description of the Invention] [Summary of the Invention] Regarding a method for manufacturing a semiconductor device, with the aim of realizing the AI pillar method stably and with good reproducibility, an aluminum pillar is placed on the lower layer wiring, and an aluminum pillar is placed on the pillar. In a method for manufacturing a semiconductor device with upper layer wiring, the lower layer wiring is copper, an aluminum layer is deposited on the copper layer, a resist pattern is formed as a mask for pillars, and the aluminum layer is formed through the resist. The method is structured to include the steps of forming pillars by reactive ion etching, then forming a resist pattern to serve as a mask for lower-layer wiring, and etching the copper layer through the resist to form lower-layer wiring.

[Industrial application field]

The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of erecting pillars for planarizing multilayer wiring.

In recent years, with the demand for higher integration of semiconductor devices, multilayer wiring technology has attracted attention, and there has been a demand for the development of planarization technology. One of the flattening techniques is the A1 pillar method.

[Conventional technology]

The pillar is the conductor that connects the lower layer wiring l and the upper layer wiring 3. In general, aluminum (Al) is deposited (vapor deposition, sputtering, etc.) for the metal for lower layer wiring, and on top of that, the same Al is deposited for the metal for pillars (if both are A1, the deposition process is done once), and A photoresist is applied on top, exposed to light using a pillar mask, developed and patterned, and the photoresist 5 is etched into the mask.In this way, pillars 2 are formed as shown in FIG. 3(b). A photoresist is applied again, exposed to light using a lower wiring mask, developed and patterned, and the photoresist is etched into the mask to form the lower wiring 1.

As described above, in the conventional AN pillar method, the lower wiring and the pillar are formed of the same type of metal (A1), and in this case, etching becomes a problem. In other words, with the same type of metal, no matter how precise the etching is, there will be excess or deficiency in the film thickness of the lower layer wiring, and as shown in FIG.
The upper surface 1a is not flat and becomes rough 61b when exposed to the etchant, as shown in FIG. 3(C).

Molybdenum (Mo) and tungsten (W) are used for the lower layer wiring.
Using high melting point metal such as or its silicide, AI
There is also a method of using a metal different from the pillar, but this also causes the same problem, albeit to a different degree.

[Problem to be solved by the invention]

As mentioned above, with conventional technology, semiconductor devices using the AI pillar method cannot be mass-produced stably and with good reproducibility.
There is also a problem that the finished shape is not desirable.

The present invention aims to improve this point and realize the A1 pillar method stably and with good reproducibility.

[Means for Solving the Problems] FIG. 1 is a diagram of a completed semiconductor device manufactured by the manufacturing method of the present invention. As mentioned above, 1 is a lower layer wiring, 2a is a pillar, 3 is an upper layer wiring, 9 is a base insulating layer, and 4 is an insulating layer between the eyebrows.

In the present invention, the lower layer wiring 1 is made of copper (Cu). The pillar 2 is made of a metal different from that of the lower layer wiring 1, for example, aluminum as in the prior art, and the upper layer wiring 3 is also made of, for example, aluminum. For example, polyimide is used for the interlayer insulating layer 4.

[Effect]

The All pillar 2 is generally formed by RIE (reactive ion etching) using the patterned photoresist 5 as a mask, but in this RIE using chlorine gas, almost no copper is etched. Not done. Therefore, by stacking the Cu layer iA1 layer 2 and etching the resulting stack with RIE using the resist 5 as a mask, and stopping the etching when the 00 layer appears, the Al pillar 2 can be precisely etched as planned. The thickness of the Cu layer 1 will not be excessive or insufficient, and the surface will not be rough.

〔Example〕

FIG. 2 shows a process example of the manufacturing method of the present invention.

As shown in FIG. 2(a), copper (Cu) is sputtered onto the base insulating layer 9 to form a copper layer 1 over the entire surface. Next, 1iJ (
Sputter aluminum as shown in bl to form A1 layer 2.
form. Next, as shown in the same figure (C1), photoresist is applied, exposed through a pillar mask, and developed to form a patterned resist 5.Next, as shown in the same figure +d), an A4 layer is formed by RIE using the resist 5 as a mask. Pillar 2 is formed by etching, and resist 5 is removed. Next, as shown in (e), photoresist is applied again.
A patterned resist 6 is produced by exposing to light through a mask for lower layer wiring and developing. Next, as shown in FIG. 6(f), the 00 layer is patterned by, for example, ion milling using the resist 6 as a mask to form the lower wiring 1.

Thereafter, polyimide, for example, is thickly applied to the entire surface, and then etched back to the top of the pillar, and then, for example, aluminum is sputtered and patterned to form the upper layer wiring 3. In this way, an element of the same (gl) is obtained, which is the first
Same as the figure.

To give an example of dimensions, the thickness of the lower layer wiring 1 is 0.5 to 0°7μ.
The thickness of m1 pillar 2 is 0.5 to 0.7 μm, and the upper layer wiring 3
The thickness is about 0.7 to 1.0 μm.

The base insulating layer 9 is generally made of silicon dioxide (S i 02
) or silicon (Si), but there is a problem in that the copper (Cu) layer l easily reacts with these. However, to counter this, a barrier metal such as titanium nitride (TiN 2 ) can be interposed between the layers 1.9.

Copper has lower resistance than aluminum and is more resistant to electromigration, so it is a promising material for interconnects in integrated circuits.

〔Effect of the invention〕

As explained above, according to the present invention, since copper is used for the lower wiring layer, etching when forming Al pillars can be easily performed with good reproducibility, and the thickness of the lower wiring can be reduced. It can eliminate surface roughness and greatly contributes to improving the mass productivity of semiconductor devices with multilayer wiring.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of a semiconductor device manufactured according to the present invention, FIG. 2 is a manufacturing process diagram showing an embodiment of the present invention, and FIG. 3 is an explanatory diagram of a conventional example. In FIG. 1, 1 is a lower wiring layer, 2 is a pillar, 3 is an upper wiring layer, and 4 is an insulating layer between the eyebrows.

Claims (1)

[Claims] 1. A method for manufacturing a semiconductor device in which an aluminum pillar is placed on a lower layer wiring and an upper layer wiring is provided on the pillar, wherein the lower layer wiring is copper and an aluminum layer is covered on the copper layer. Then, form a resist pattern that will serve as a mask for the pillar, perform reactive ion etching on the aluminum layer through the resist (5) to form the pillar (2), and then form a resist pattern that will serve as a mask for the lower layer wiring. A method for manufacturing a semiconductor device, comprising the step of etching the copper layer through the resist (6) to form a lower wiring (1).