JPS636847A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS636847A JPS636847A JP15041786A JP15041786A JPS636847A JP S636847 A JPS636847 A JP S636847A JP 15041786 A JP15041786 A JP 15041786A JP 15041786 A JP15041786 A JP 15041786A JP S636847 A JPS636847 A JP S636847A
- Authority
- JP
- Japan
- Prior art keywords
- film
- metal
- metallic
- wiring layer
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体装置の製造方法に関し、特にその金
属配線の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing metal wiring thereof.
第2図は従来の半導体装置の金属配線の製造方法を示す
工程別断面図である。FIG. 2 is a cross-sectional view showing each step of a conventional method for manufacturing metal wiring for a semiconductor device.
以下これを用いて従来の半導体装置の製造方法を説明す
るっ
まず、第2図(a) K示すようにシリコン基板(1)
の主面上にスムースコートIII [2)を化学的気相
成長法(以下CVD法と称する)スピンコード法などに
より形成した後、写真製版及びエツチング法により所定
のコンタクト穴(3)を形成するっ次に第2図(b)に
示すように上記スムースコート膜(2)及びコンタクト
穴(3)上に、スパッタ法、蒸着法などにより金属膜(
4)を形成する。Below, we will explain the conventional manufacturing method of a semiconductor device using this.First, as shown in FIG. 2(a), a silicon substrate (1) is used.
After forming a smooth coat III [2) on the main surface of the substrate by a chemical vapor deposition method (hereinafter referred to as CVD method) or a spin code method, predetermined contact holes (3) are formed by photolithography and etching. Next, as shown in FIG. 2(b), a metal film (
4) Form.
次いで第2図(C)に示すように上記金属膜(4)を写
真製版及びエツチング法により加工して金属配線(5)
を形成する。Next, as shown in FIG. 2(C), the metal film (4) is processed by photolithography and etching to form metal wiring (5).
form.
従来の半導体装置の製造方法では以上のように金属配線
を形成するため、この金属配線を被覆する図示しない保
護俟に金属配線による段差が生じ、多層配線の際この段
差部で配線幅の細りゃ断線が発生しやすく、また、微細
化に伴ない配線幅が細くなるにつれて、配線の安定性が
劣化するなどの問題点があった。In the conventional manufacturing method of semiconductor devices, metal wiring is formed as described above, so that a step is created by the metal wiring in the protective layer (not shown) that covers the metal wiring, and when multilayer wiring is performed, the wiring width becomes thinner at this step. There have been problems in that wire breaks are likely to occur, and as the wiring width becomes narrower with miniaturization, the stability of the wiring deteriorates.
この発明は上記のような問題点を解消するためになされ
たもので、段差がない金属配線を修改できる半導体装置
の製造方法を得ることを目的とする0
〔問題点を解決するだめの手段〕
この発明に係る半導体装置の製造方法は電極敗り出し穴
上に設けられた溝及び絶縁膜上知金属被膜を形成する工
程、この金属被膜上及び絶縁膜上にレジストを塗布し、
この金属被膜及びレジストをこれらが同等のエツチング
速変となるエツチング条件でエツチングするようにした
ものであるう〔作用〕
この発明における半導体装置の製造方法は、絶縁膜に形
成した溝の中に金属被膜を埋め込むことにより、段差が
ない金属配線が形成できる。This invention has been made to solve the above-mentioned problems, and its purpose is to provide a method for manufacturing a semiconductor device that can repair metal wiring without steps.0 [Means for solving the problems] The method for manufacturing a semiconductor device according to the present invention includes a step of forming a groove provided on an electrode break-out hole and an insulating film, a metal film, and applying a resist on the metal film and the insulating film.
The metal film and the resist are etched under etching conditions that give the same etching speed. By embedding the film, metal wiring without steps can be formed.
第1図はこの発明の一冥施例による半導体装置の製造方
法を示す工程別断面図であるっまず、第1図(a)に示
すように従来法と同様にしてスムースコー)@(2)は
コンタクト穴(3) fr形放するうただし本冥施例で
はこのコンタクト穴(3)はシリコン基板(1)まで達
しなくともよく、所定の深さまで形成すればよい。次に
第1図価)K示すように再度写真製版及びエツチング法
によりスムースコート膜(2)のコンタクト穴(3)部
分に配線用の溝(6)全形成するっこの配線用の溝(6
)を形成するためのエツチングによって上記コンタクト
穴(3)がシリコン基板(1)まで達するようにコンタ
クト穴(3)及び配線用の溝(6)を形成するためのエ
ツチング条件を選ぶ。FIG. 1 is a cross-sectional view of each step showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. First, as shown in FIG. ) is a contact hole (3) which is a contact hole (3). However, in this embodiment, this contact hole (3) does not need to reach the silicon substrate (1), but may be formed to a predetermined depth. Next, as shown in Figure 1), a wiring groove (6) is completely formed in the contact hole (3) portion of the smooth coat film (2) by photolithography and etching again.
) The etching conditions for forming the contact hole (3) and the wiring groove (6) are selected so that the contact hole (3) reaches the silicon substrate (1).
火に第1図(c)に示すようにスパッタ法、蒸着法など
により金属膜(4)を形成し、該金属膜(4)上にスピ
ンコード法などによりホトレジスト(7)を形成する0
次に第1図(d)に示すように上記ホトレジスト(7)
と金属H(4) ? 、両者のエツチング速変がほぼ等
しくなる条件でエツチングしくエッチバック)、金属配
線(5)をスムースコー)[f2)に形成した配線用の
溝(6)に埋め込まれた形で形成するっ最後に第1図(
e)に示すように金属配線(5)上に残ったホトレジス
ト(7)を除去するっ
こつように、金属配線(5)をスムースコート膜(2)
に埋め込んで形成することにより段差のない、しかも安
定な金属配線を形成できる半導体装置の製造方法を得る
ことができる。As shown in FIG. 1(c), a metal film (4) is formed on the metal film (4) by a sputtering method, a vapor deposition method, etc., and a photoresist (7) is formed on the metal film (4) by a spin code method, etc. As shown in FIG. 1(d), the above photoresist (7)
and metal H(4)? , the metal wiring (5) is etched back under the conditions that the etching speed change of both is almost equal), and the metal wiring (5) is formed embedded in the wiring groove (6) formed in the smooth surface (f2). Figure 1 (
As shown in e), the metal wiring (5) is coated with the smooth coating film (2) to remove the photoresist (7) remaining on the metal wiring (5).
By embedding and forming the metal wiring in the semiconductor device, it is possible to obtain a method of manufacturing a semiconductor device that can form a stable metal wiring without a step.
なお、上記−大施例では、シリコン基板(1)と直接コ
ンタクlfsる金属配線について示したが、多層配線構
造の半導体装置においては全ての金属配線について同様
の効果が期待できる。In the above-mentioned large example, the metal wiring in direct contact with the silicon substrate (1) was shown, but similar effects can be expected for all metal wiring in a semiconductor device with a multilayer wiring structure.
また、上記−芙施11t’lではエッチバックの際にホ
トレジスト(7)を用いた場合について説明したが、金
属膜(4)上にモ坦性を持たせて形成でき、かつ金属膜
と同程度の速変でエツチングできる他の物質を用いた場
合にも同様の効果が期待できる。In addition, although the case where the photoresist (7) is used during etchback is explained in the above-mentioned section 11t'l, it can be formed on the metal film (4) with flatness and is the same as the metal film. A similar effect can be expected when using other materials that can be etched at a relatively rapid rate.
さらK、金属配線(5)に用いられる材料は半導体、ア
ルミニウム、アルミニウム合金、高触点合金、高触点金
属のシリサイドのいずれか、又はそれらの混合物から適
宜、選択できる。Furthermore, the material used for the metal wiring (5) can be appropriately selected from semiconductors, aluminum, aluminum alloys, high contact point alloys, silicides of high contact point metals, or mixtures thereof.
以上のように、この発明によれば電極取り出し穴上に設
けられた溝及び絶縁膜上に金属被膜を形成する工程、こ
の金属被膜上及び絶縁膜上にレジストを塗布し、この金
属被膜及びレジストをこれらが同等のエツチング速實と
なるエツチング条件でエツチングするようにしたので、
段差がない金属配線を得ることができるという優れた効
果を有する。As described above, according to the present invention, there is a step of forming a metal coating on the groove provided on the electrode extraction hole and the insulating film, applying a resist on the metal coating and the insulating film, and applying the resist on the metal coating and the insulating film. Since these were etched under etching conditions that resulted in equivalent etching speed,
It has the excellent effect of being able to obtain metal wiring without steps.
第1図はこの発明の一冥施例による半導体装置の製造方
法を示す工程別断面図、第2図は従来の半導体装置の製
造方法を水中工程別断面図である。
(1)はシリコン基板、(2):吐スムースコート膜、
(3)はコンタクト穴、(5)は金属配線、(6)は配
線用の溝、(7)はレジストであるっ
なお、図中、同一符号は同一、又は相当部分を示す。
第1図
第2図
(b)
手続補正書(自発)
昭和 年 月 日
2、発明の名称
半導体装置の製造方法
3、補正をする者
代表者志岐守哉
6、補正の対象
明細書の発明の詳細な説明の欄
6、補正の内容FIG. 1 is a step-by-step sectional view showing a semiconductor device manufacturing method according to an embodiment of the present invention, and FIG. 2 is an underwater step-by-step sectional view of a conventional semiconductor device manufacturing method. (1) is a silicon substrate, (2) is a discharged smooth coat film,
(3) is a contact hole, (5) is a metal wiring, (6) is a groove for wiring, and (7) is a resist. In the drawings, the same reference numerals indicate the same or corresponding parts. Figure 1 Figure 2 (b) Procedural amendment (voluntary) Showa year, month, day 2, title of the invention: Method of manufacturing a semiconductor device 3, representative of the person making the amendment: Moriya Shiki 6, invention of the specification subject to the amendment Detailed explanation column 6, content of amendment
Claims (2)
絶縁膜に電極取出し穴及びこの電極取出し穴上に溝を形
成する工程、この溝及び絶縁膜上に金属被膜を形成する
工程、この金属被膜上及び絶縁膜上に、レジストを塗布
する工程、この金属被膜及びレジストをこれらが同等の
エッチング速度となるエッチング条件でエッチングする
工程を含む半導体装置の製造方法。(1) A step of forming an insulating film on the surface of a semiconductor substrate, a step of forming an electrode extraction hole in the insulating film and a groove on the electrode extraction hole, a step of forming a metal coating on the groove and the insulating film, A method for manufacturing a semiconductor device, which includes a step of applying a resist on a metal film and an insulating film, and a step of etching the metal film and the resist under etching conditions such that the metal film and the resist have the same etching rate.
ム合金、高融点金属、高融点金属のシリサイドのいずれ
か、又はそれらの混合物であることを特徴とする特許請
求の範囲第1項記載の半導体装置の製造方法。(2) The semiconductor device according to claim 1, wherein the metal film is a semiconductor, aluminum, an aluminum alloy, a high melting point metal, a silicide of a high melting point metal, or a mixture thereof. Production method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15041786A JPS636847A (en) | 1986-06-26 | 1986-06-26 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15041786A JPS636847A (en) | 1986-06-26 | 1986-06-26 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS636847A true JPS636847A (en) | 1988-01-12 |
Family
ID=15496484
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15041786A Pending JPS636847A (en) | 1986-06-26 | 1986-06-26 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS636847A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5091339A (en) * | 1990-07-23 | 1992-02-25 | Microelectronics And Computer Technology Corporation | Trenching techniques for forming vias and channels in multilayer electrical interconnects |
| US5173442A (en) * | 1990-07-23 | 1992-12-22 | Microelectronics And Computer Technology Corporation | Methods of forming channels and vias in insulating layers |
-
1986
- 1986-06-26 JP JP15041786A patent/JPS636847A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5091339A (en) * | 1990-07-23 | 1992-02-25 | Microelectronics And Computer Technology Corporation | Trenching techniques for forming vias and channels in multilayer electrical interconnects |
| US5173442A (en) * | 1990-07-23 | 1992-12-22 | Microelectronics And Computer Technology Corporation | Methods of forming channels and vias in insulating layers |
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