JPH01282925A - Counter device - Google Patents

Abstract

PURPOSE:To obtain a required operating speed with a required minimum chip area by providing a detection circuit detecting the carrying to a high-order counter without awaiting a carry signal from a low-order counter. CONSTITUTION:A counter circuit 8 is divided into two counters corresponding to high-order 4-bit for a high-order counter and to low-order 4-bit for a low- order counter. D flip-flops F0-F3 start counting by a clock signal sequentially. A domino circuit 5 detects an output data in the D flip-flops F0-F3, and when all low-order 4-bit is counted finally, N-channel field effect transistors 41-43 being components of the domino circuit 5 are all turned on. A count detection circuit 6 brings a count signal inputted to the high-order 4-bit to an H level and count the high-order 4-bit as soon as the low-order 4-bit is counted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a counter device comprising a ripple counter with improved speed.

[Conventional technology]

Figure 4 shows, for example, "M08LS" published by Sangyo Tosho Co., Ltd.
1 is a circuit diagram showing a counter device using a conventional ripple counter published in ``Introduction to I Design''.

In the figure, Fo#F, a D flip 70 and 41 that constitute the beam tuple counter, are input terminals to which a clock signal CLK is input. FIG. 5 is a circuit diagram showing a counter device using a control chain counter.

In the figure, the same parts as in FIG. 4 are given the same reference numerals. 1
3x and 1h are AND gates forming a control chain.

Now, in FIG. 4, the clock signal CLK is input from the input terminal 41 to the terminal φ of the flip-flop D7. , the output data is input from the Qa terminal to the terminal φ1 of the next D flip-flop F1. In this way, the next D7 lip-flops F2eF3...K are sequentially transmitted and a counter operation is performed. Therefore, since each 071J round flop operates by sequentially inputting the output of the D flip-flop connected before it, the operating speed of the ripple counter is controlled by the propagation speed of the D flip-flop.

Also, in FIG. 5, the clock signal CLK is supplied to each D flip-flop through the input terminal 41. and,
Only when there is output data at the terminal Q0 of the D flip-flop Fo and the terminal Q1 of the D flip-flop F1, the D
flip flop F.

Output data is input from the terminal T of the KAND gate 131. Next, the terminal Q! of the D flip-flop F2! The output data is input to the AND gate 131. In this way, the signal is sequentially transmitted to the next D flip-flop Fs to perform the counter operation.

Therefore, the operating speed of the ripple quanta is governed by the propagation speed of the AND gate for the control chain.

[Problem to be solved by the invention]

However, in the conventional force converter device shown in FIG. 4, since the D flip-flops operate sequentially, the operating speed of the ripple counter is slow and a counter capable of high-speed operation cannot be obtained. In addition, in the case of the Kawanta device shown in Fig. 5, the Kawanta operating speed is high, but the number of gate inputs to the AND gate is large, which increases the chip area of the integrated circuit that forms this Kawanta. The regularity of the resulting pattern deteriorated, making the design complicated.

The present invention has been made to solve the above-mentioned table defects, and it is possible to obtain the desired quantization speed with the minimum necessary chip area, and also to be able to arbitrarily select the number of bits to be divided.
It is an object of the present invention to obtain a kakunta device which has good regularity and allows easy pattern design.

[Means to solve the problem]

In order to solve the above-mentioned drawbacks, the present invention includes a detection circuit that detects the 9th timing of a carry from a lower quanta to an upper quanta without waiting for multiple signals.

[Effect]

The upper-order quanta performs a carry operation without waiting for the carry 9 signal from the lower-order side by the detection circuit.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

This circuit company has an 8-pitsu triple pull-up power Kunta circuit.
The upper 4 bits correspond to the upper quanta and the lower 4 bits correspond to the lower quanta, each of which is divided into two kakuntas. In the figure, 1 is a P-type field effect transistor, 2 is a ground terminal, F, #F is a D7 lip-flop, and 5 is a D7 lip-flop). Domino circuit 6 is the upper side 4 when domino circuit 5 is turned on.
A quant detection circuit detects that a bit carries up and generates a quant signal CTS corresponding to a carry signal to the upper 4 bits, T is an input terminal to which the clock signal CLK is input, and 8 is an inverted signal Q1 of the clock signal CLK. 9 is a P-type field effect transistor connected to the power supply terminal 12, and 10 is a quant detection circuit 6.
This is an output terminal that outputs the quant signal CTS from the . Moreover, FIGS. 2(a) to 2(e) are time charts for each part of FIG. 1. (1) in the same figure shows the clock signal CL.
(b) is a quant diagram of the lower 4 bits, (c) is a level waveform diagram of point n, (d) is a waveform diagram of the quant signal CTS, (e) is a waveform diagram of K. shows the quant diagram of the upper 4 bits.

Next, the operation will be explained. First, similar to the ripple counter shown in FIG. 4, the cyclic clock signal CLK from the input terminal 1 is input to the first D71J and 70F. Next, the output data is output from the terminal Qo and input to the terminal φ1 of the next D7'J block 70 block F. In this way, the signal is sequentially transmitted to the next D-flip 70 to perform a counter operation.

On the other hand, the domino circuit 5 has each D clip 70 tubes F.

~Detect output data of terminal Qo=Qs in F3,
When all the lower 4 bits are quantized to the end, the N-type field effect transistors 41 to 4 forming the domino circuit 5
3 are all turned on. Therefore, the level at point a, which had been at the rHJ level through the P-type field effect transistor 9, becomes the rLJ level as shown in FIG. 2(C). At this time, the count detection circuit 6 detects this rLJ level, and at the same time as the rising edge of the next clock signal CLK is input (FIG. 2(a)), the upper side 4
The quant signal CTS input to the bit is set to the 1-H level ((d) in the same figure). Then, at the same time as the lower four bits perform a counting operation, the upper four bits are caused to perform a counting operation ((e) in the same figure).

In this way, if the upper 4 bits of K can perform counter operation without waiting for a carry signal from the lower 4 bits, the counter operation speed will be improved.

In addition, in the above-mentioned embodiment, the number of bits is set to 2 on the upper side and 2 on the lower side.
Although a divided ripple up counter has been described, the number of divisions may be increased if the counter has a large number of bits or if it is desired to further speed up the counter operation. FIG. 3 is a circuit diagram showing another embodiment in which the number of bits to be divided is increased.

In the figure, the same parts as in FIG. 1 are given the same reference numerals. 16 is an inverting logic circuit connected to the gate of P-type field effect transistor 1, 5 & is a domino circuit which also serves as N-type field effect transistors 44 to 4n, F4 to F'n+l
is a D flip-flop.

In this case, the carry signal from the lower counter to the middle counter is detected by the count detection circuit 6, and the P-type field effect transistor is turned on via the inverting logic circuit 16. Therefore, count detection from the lower side to the middle side can be performed continuously, and furthermore, the count detection can be transmitted to the upper side count.

Further, since the ripple up counter is divided by the count detection circuit 6, it is possible to facilitate the counter operation test.

〔Effect of the invention〕

As explained above, the present invention is equipped with a detection circuit that detects a carry operation to the upper side counter without waiting for a carry signal from the lower side counter. operation speed can be obtained. Furthermore, since the circuit configuration is simple, design is easy, and pattern design can be simplified, which has remarkable effects.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing one embodiment of the present invention, FIG. 2 is a time chart of each part, and FIG. 3 is a circuit diagram showing another embodiment in which the number of bits to be divided is increased. FIG. 4 is a conventional circuit diagram, and FIG. 5 is a circuit diagram of a conventional control chain counter. 1.9...P-type field effect transistor, 2...
Ground terminal, 4t~44...N-type field effect transistor, No. 5, domino circuit. 6...Sound detection circuit, 7.8...Input terminal, 10...Output terminal.

Claims (1)

[Claims] In a ripple counter that performs a counting operation based on a carry signal from a lower counter to an upper counter, the timing of a carry to the upper counter is determined without waiting for a carry signal from the lower counter. A counter device comprising a detection circuit for detecting.