JPH0198320A - Counter circuit - Google Patents

Abstract

PURPOSE:To reduce the time to start the measurement by providing a basic signal switching circuit outputting a basic signal with/without inversion depending on the state of the basic signal in receiving a measurement start signal. CONSTITUTION:In receiving a measurement start signal X0 with a basic signal phi0 at a low level (L), a counter 1 is reset to be in the state of awaiting of measurement. Then an N-channel transistor(TR) 61 in a 1-bit latch circuit 6 is turned on and the state of the signal phi0 is read and an output signal X1 of the circuit 6 goes to an L level. Thus, the output signal phi2 of the NAND gate 53 receiving the signal X1 goes to a high level (H), a signal being the result of inversion by the inverter 54 receiving the signals phi0 and X1, that is, the output signal phi1 of the NAND gate 52 receiving the H level is a signal being the inversion of the signal phi0. Thus, the output signal phi3 of the NAND gate 51 is the signal phi0 and the measurement is started from a time within a half period (T/2) of the signal phi0 from a time t2.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a counter circuit.

[Conventional technology]

Figure 3 is a circuit diagram of a conventional counter circuit, Figure 4 (1),
(2) is a time chart showing the operation.

This counter 1 is a plurality of flip-flops '1 + 1
2 +...+ln, which is reset when the measurement start signal xo is input from the control signal input line 3, and starts counting the basic signal φ0 from the subsequent first rise of the basic signal φ0 from the basic signal input line 2. Start (Figure 4 (1),
(2)).

[Problem that the invention seeks to solve]

In the conventional counter circuit described above, the basic signal is directly input, and the measurement start signal x generated at an arbitrary timing is
Basic signal φ after o is input.

Since counting starts from the first rise of , there is a drawback that it takes at most one cycle of the basic signal φ0 from the time the measurement start signal XO is input until the counting actually starts.

[Means for solving problems]

The counter circuit of the present invention inputs a measurement start signal and a basic signal, and is configured so that, depending on the state of the basic signal when the measurement start signal is input, a potential change in the basic signal immediately after starts the counter operation. It has a basic signal switching circuit that inverts the basic signal or outputs it to the counter without inverting it.

[Effect]

Therefore, the time from when the measurement start signal is input to when measurement actually starts is at most 1I2 periods of the basic signal.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of one embodiment of the counter circuit of the present invention, and FIGS. 2 (1) and (2) are time charts showing its operation.

In this embodiment, a basic signal switching circuit 4 consisting of a gate circuit group 5, a bit latch circuit 6 is added to the conventional counter circuit shown in FIG. This basic signal switching circuit 4
is the fundamental signal φ. and the measurement start signal Xo are input, and when the basic signal φ0 is low level when the measurement start signal x0 is input, the basic signal φ. is output to the counter 1 as is, and when the basic signal φ0 is at a high level when the measurement start signal XO is input, the basic signal φ0 is inverted and output to the counter 1. Gate circuit group 5 is Nantes gate 51~
53 and inverters 54+55, and the 1-bit latch circuit 6 consists of an N-channel transistor 6I and inverters 62+63. The gate of the N-channel transistor 61 is connected to the control signal input line 3 to which the measurement start signal X6 is applied, and the source is the basic signal φ. Basic signal input that is applied! ! 2 is connected to the output terminal of the inverter 55 whose input terminal is connected, and its drain is commonly connected to the output terminal of the inverter 62 and the input terminal of the inverter 63. The input terminal of the inverter 62 and the output terminal of the inverter 63 are commonly connected and serve as an output signal line of the 1-bit latch circuit 6. The output signal x of the 1-bit latch circuit 6 is generated by the basic signal φ0 and the inverter 54.
A Nantes gate 5 to which a signal x1 in which 1 is inverted is input.
2 converts the signal φ1 which is the NAND of these signals into the basic signal φ by the inverter 55. The Nant gate 53 to which the signal To inverted and the output signal X1 of the 1-bit latch circuit 6 is input outputs the NAND of these signals φ2 to the Nant gate 5I, and the Nant gate 51 outputs the signal φ1 and the signal φ2. A signal φ3, which is the NAND of , is output to the counter 1.

Next, the operation of this embodiment will be explained with reference to FIGS. 2(1) and (2).

(1) Measurement start signal X0 when basic signal φ0 is low level
is input (Fig. 2 (1)).

Time 1. When the measurement start signal X6 is input to the counter l
is reset and enters a measurement waiting state until the rising waveform of the basic signal φ0 is input, and at the same time, the N-channel transistor 61 in the 1-bit latch circuit 6 is turned on, the state of the basic signal φ0 is read, and the 1-bit latch circuit 6 The output signal x1 of becomes low level. Therefore, the output signal x
The output signal φ2 of the Nandts gate 53 to which 1 is input becomes a high level, and the output signal φ2 of the Nandts gate 52 to which a high level is inputted is the basic signal φ0 and the signal x3 obtained by inverting the output signal X1 by the inverter 54. becomes the signal T0 which is the inversion of the basic signal φ0, so the output signal φ3 of the Nantes gate 51 which performs the NAND operation of these becomes the basic signal φ0, and from time t2, the 1I2 of the basic signal φ0
Measurement starts from time t3 within period T/2.

(2) When the measurement start signal XO is input when the basic signal φ0 is at a high level ((2) in FIG. 2).

When the measurement start signal x0 is input at time t, as shown in FIG.
Similarly to case 1), the output signal x1 of the 1-bit latch circuit 6 becomes high level, and the signal xl obtained by inverting the output signal xl, that is, the output signal φl of the Nant gate 52 to which the low level is input, becomes high level, and the output signal x
The output signal φ2 of the Nandts gate 53, which receives a non-zero value obtained by inverting I and the basic signal φ0 by the inverter 55, becomes the basic signal φ0, so the output signal φ3 of the Nandts gate 5I, which takes the NAND of these, becomes the basic signal φ0. 172 cycles T of the basic signal φ0 from time t1
Measurement starts from time t2 within /2.

Note that the time 1. shown by diagonal lines in FIGS. 2(1) and (2). The output XI of the previous 1-bit latch circuit 6,
The outputs φ1 to φ3 of the Nandt gates 51 to 53 are indeterminate and do not affect the operation of this embodiment in any way.

Furthermore, although the counter of this embodiment has been described as starting measurement from the rising edge of the basic signal φ0, when it operates at the falling edge of the basic signal φ0, the input to the Nant gate 52 is
Below the signal with inverted 0. and the output signal X of the 1-bit latch circuit 6! and the input to the Nant gate 53 is the basic signal φ
If the output signal x1 of the 0 and 1 bit latch circuit 6 is an inverted signal x1, the time from when the measurement start signal XO is input until the measurement actually starts is 1/2 of the basic signal φ0 in any case. The period is within T/2.

〔Effect of the invention〕

As explained above, the present invention provides a basic signal switching circuit that inverts or outputs the basic signal depending on the state of the basic signal when the measurement start signal is input. The time from when the signal is received to the actual start of measurement is at most 1/2 cycle of the basic signal, which has the effect of shortening the start time of measurement.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of one embodiment of the counter circuit of the present invention, Fig. 2 (1) and (2) are its time charts, Fig. 3 is a circuit diagram of a conventional example of the counter circuit, and Fig. 4 (1) ) and (2) are the time charts. 1...Counter, 1,~1n...Flip-flop, 2...Basic signal input line, 3...Control signal input line, 4...Basic signal switching circuit, 5...Gate circuit group. 51-53...Nant Gate, 54 I 55.62.63...Inverter, 6...
・1-bit latch circuit, 61...N-channel transistor, φ0...basic signal, XO...measurement start signal, xl...output signal of 1-bit latch circuit 6, φl...
- Output signal of Nantes gate 52, φ2...output signal of Nantes gate 53, φ3...output signal of Nantes gate) 5+.

Claims (1)

[Claims] In a counter circuit that receives a measurement start signal and a basic signal and starts counting the basic signal from the first rising or falling time of the basic signal after the measurement start signal is input and reset, the measurement start signal and the basic signal are input. signal, and depending on the state of the basic signal when the measurement start signal is input, the basic signal is inverted so that the potential change of the basic signal immediately after starts the counter operation, or it is not inverted. A counter circuit that has a basic signal switching circuit that outputs to the counter.