JPH01282940A - Memory clear method - Google Patents

Abstract

PURPOSE:To clear the memory independently in the component by providing a means setting the transfer direction of read/writhe independently of a bus node in a component of the bus node. CONSTITUTION:A head address of a memory area to be cleared in an address generating circuit ADG at first and a byte number desired to be cleared is set to a control circuit CNT and the transfer direction of a data is set to a bus node 1 as the read direction by using a control signal S1. When the node 1 is started from CPU 7, since the node 1 is set in the read direction, the data is in the input mode and the memory is also in the input mode and all data buses DB go to a high level by a pullup resistor R. As a result, the CNT writes the data of high level to the memory by the number designated from the designated address to clear the memory.

Description

[Detailed Description of the Invention] [Summary] Regarding a memory clear method in a data synchronous transfer method for a network in which a plurality of bus nodes are connected in a ring shape, the present invention clears the memory independently of block transfer via the bus nodes. Improving ring bus usage efficiencyC
The purpose of this system is to reduce the load on the PU, and it has a plurality of bus nodes connected in a ring shape by a ring bus and a component connected to each of the bus nodes, and data is transferred in blocks in one direction between the bus nodes. A memory clearing method in a synchronous transfer method, wherein the component includes a control means for controlling read/write timing to the bus node and the memory, and the transfer direction of the bus node and the transfer direction of the memory connected thereto are independent. The transfer direction control means sets the memory in a write direction based on a command from a CPU, and sets the bus node in a read direction to write and clear the memory. Configure.

[Industrial application field]

The present invention relates to a memory clearing method, and in particular, when transferring a large amount of data such as image data between multiple devices at high speed, a network is configured in which multiple bus nodes are connected in a ring shape, and the data of each bus node is converted into block data. This paper relates to a memory clearing method in a data synchronous transfer method that sequentially transfers blocks in parallel and synchronously to adjacent nodes.

[Conventional technology]

FIG. 3 is a basic configuration diagram of the data synchronous transfer method. 2 is a ring bus that connects each bus node, 3 is a data bus that forms part of ring bus 2, and 4 is a control that forms part of ring bus 2. 5 is a process identification bus forming part of the ring bus 2; 6 is a component C8 as a system component connected to the bus node;
C6 and C7 are CPUs that control the system.

In such a basic configuration, the data bus 3 performs block transfer of data, but its format is a bus for sequential data transfer, and the transfer direction is constant in a series of data transfers. Therefore, three operating modes are required as basic modes for transfer control: output mode, input mode, manual power mode, and bus mode. In the output mode, an empty token indicating non-use of the data bus from the previous stage bus node is input, and manually generated data from the memory of the component connected to the own bus node is generated on the bus.

Then, the data sent from the own bus node is transferred to the ring bus 2.
This is obtained by going all the way around and being manually powered from the previous stage. Further, the input mode is set for one-to-one transfer, and when a bus node set to this mode receives data of a specified process from a previous stage bus node, it acquires the data and outputs it to the component. Furthermore, the manual and bus modes are set in multi-drop transfer, and when a bus node set to this mode receives data from the specified process from the previous bus node, it outputs that data to the component and also to the subsequent bus node. Forward.

In addition, each bus node has a transfer buffer inside, and a bus node set to output or input mode can suspend or resume transfer for the output bus node depending on the available capacity of the transfer buffer specified by the CPU 7. Generate a controlling token on the bus.

FIG. 4 shows an example of a conventional component configuration. The bus node 1 is one of the bus nodes N0 to N in FIG. 3, and the component 6 is one of the bus nodes C0 to C5. Component 6 includes a memory M having a human capacity for transferring a large amount of data at high speed, an address generation circuit ADG for setting a start address, and an I for data transfer direction, etc.
) It has a control circuit CNT that performs MA control. Further, R provides a data bus Ds+l:g flow. This is Brua Rib resistance.

Clearing of the memory M is performed as follows. That is, first,
After setting the read/write direction in the bus node 1 and then setting the start address ADD in the address generation circuit ADG, the bus node 1 is activated to perform an arbitrary number of transfers from an arbitrary address on the memory at high speed. Memo IJ
Access to M is controlled by a handshake signal from bus node 1, and transfer direction indication signal S from bus node 1
Read/write control is performed by 0. The transfer source bus node is activated in the same way, data is written to memory M, and memo 'JM is cleared. Transfer direction indicating signal S in this case. indicates the above-mentioned operation mode, and has flags indicating each mode. In addition, control signals S1 and S
2 is for controlling the transfer timing of bus nodes and memory.

[Problems to be Solved by the Invention] As described above, in this type of system, there is a problem in that the memory can only be cleared by data transfer from another bus node. In other words, for example, when switching tasks, it is necessary to clear all memory contents to prevent malfunctions, but in such a ring-shaped system, the CPU cannot directly clear the memory, and the CPU on the bus This is done by temporarily storing erase data, for example "00...0" in a memory adjacent to the memory, and then transferring this data as a block to the memory to be cleared via a bus and a bus node. Therefore, memory is cleared only by data transfer on the bus, and in this case, buses and bus nodes other than the memory to be cleared must also be activated. Therefore, the processing amount of the CPU for this increases, and there is also the problem that bus nodes other than those on the side of the memory to be cleared cannot perform other transfers while the JA is being performed.

An object of the present invention is to solve the above-mentioned problem that when the CPU clears memory, it can only clear it by data transfer from another bus node. The purpose of this invention is to provide a means for setting the memory, and to enable the memory to be cleared independently within the component, thereby reducing the burden on the CPU and improving the usage efficiency of the bus node.

[Means and operations for solving the problems] FIG. 1 is a block diagram of the principle of the present invention.

As shown in the figure, the present invention has a plurality of bus nodes (1) connected in a ring shape by a bus (2), and a component (6) connected to each of the bus nodes, with a unidirectional connection between the bus nodes. A memory clearing method in a data synchronous transfer method that performs block transfer at a time, wherein the component includes a control means (CNT) for controlling read/write timing to the bus node and the memory.
and transfer direction setting means (RG) for independently setting the transfer direction of the bus node and the transfer direction of the memory (M) connected thereto, and the transfer direction control means includes a CPU
The present invention is characterized in that the memory is set in the write direction based on the command in (7), and the bus node is set in the read direction, thereby writing to and clearing the memory.

〔Example〕

FIG. 2 is a block diagram of an embodiment of the memory clear method according to the present invention. In the figure, RG is a register consisting of, for example, a plurality of flip-flops for reading/writing the memory. As shown, by adding register RG to the conventional configuration shown in FIG. 4, memory can be cleared within component 6 independently of the bus node.

Register RG has a function to set the transfer direction of read or write, and by setting the transfer direction of bus node 1 and memory M in the opposite direction as read to bus node 1 and write to memo IJM and start, memory IJ Clear M. As mentioned above, conventionally, reading/writing of the memory IJM was switched by the transfer direction indicating signal So from the bus node 1.

To clear memory using this method, first address generation circuit A
Set the start address ADD of the memory area you want to clear in DG, then set the number of bytes you want to clear in control circuit CNT (
The number of words) is set, and the data transfer direction for bus node 1 is set as the read direction by control signal SI. Also, write command S from the CPU is stored in register RG.
The write direction is set and the bus node 1 is activated.

At this time, bus node 1 is set in the read direction, so it becomes a manual mode overnight, and the memory also becomes an input.
The data bus DB is all brought to a high level by the pull-up resistor R. Since the control circuit CNT is set to the write state by the control signal Ss from the register RG, it transfers all high-level data from the specified address to the specified number of memories while handshaking with bus node 1 on the data bus DB. Write. As is clear, the transfer direction indicating signal So from the conventional bus node is no longer necessary, but this signal S. It may also be used when providing a membrane protection circuit to prevent the outputs from the transfer buffer and the bus node from colliding. Furthermore, the end of clearing (end of write operation) is notified to the CPU in the same way as the end of normal transfer.

〔Effect of the invention〕

As explained above, according to the present invention, by adding a register to set the read/write transfer direction, memory can be cleared independently within a component without being cleared via a bus node. ,
The usage efficiency of bus nodes can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a block diagram of an embodiment of the present invention, FIG. 3 is a basic configuration diagram of a data synchronous transfer system, and FIG. 4 is a conventional configuration diagram. (Explanation of symbols) 1...Bus node, 2...Ring bus, 3
...f'-tabus, 4...control bus, 5...process identification bus, 6...component, 7...CPU, M...memory,
ADG: Address generation circuit, CNT: Control circuit, RG: Memory read/write register.

Claims (1)

[Scope of Claims] A plurality of bus nodes (1) connected in a ring shape by a bus (2), and a component (6) connected to each of the bus nodes, wherein blocks are unidirectionally transferred between the bus nodes. A memory clearing method in a data synchronous transfer method that performs a data synchronous transfer method, wherein the component includes a control means (CNT) that controls read/write timing to the bus node and the memory, and a control means (CNT) that controls the transfer direction of the bus node and is connected to the control means (CNT). The transfer direction setting means (RG) independently sets the transfer direction of the memory (M), and the transfer direction control means sets the memory in the write direction based on a command from the CPU (7) and reads the bus node. A memory clearing method that writes to and clears the memory by setting the direction.