JPH01286552A - Signal processing system - Google Patents

Abstract

PURPOSE:To allow an intermediate relay station to branch and insert an additional bit easily by devising the system such that a specific additional bit is arranged in the same string at equal intervals even after converting the string to some string. CONSTITUTION:In the case of inserting an additional bit to a data signal inputted from a carrier terminal station equipment, processing framing and applying conversion to a string for the transmission to a radio line, the length of a subframe to a prescribed position whose additional bit is inserted is formed to be a product among the number of strings before string conversion, the number of strings after string conversion and an optional natural number. Thus, the specific additional bit is branched or inserted easily in the intermediate relay station and the equipment of the intermediate relay station is simplified and the cost is reduced.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a signal processing method, and in particular to signal processing for converting the structure of a data signal input from a carrier terminal device into a structure suitable for transmission over a wireless line. Regarding the method.

[Conventional technology]

When transmitting a data signal input from a carrier terminal equipment over a wireless line, in order to insert additional bits for monitoring and controlling the wireless line, the input data signal is speed-converted at high speed and the time for the additional bits is set. A slot is created, various additional bits are inserted into this time slot, and a frame is created. When the input data signal has multiple columns, each column is not necessarily synchronized, so stuff bits are inserted as necessary to synchronize each column. Stuff bits are also inserted at fixed positions in the frame in the same way as the additional bits described above. however,
This fixed position bit may be a stuff bit or an information bit (in the input data signal).

If the wireless line uses a 21-value (l is an integer of 2 or more) multilevel modulation, it is necessary to send four columns of data signals to the wireless line. When the number of columns k of the data signal input from the carrier terminal equipment does not match l, it is necessary to convert the columns into one column.

Speed conversion and additional bit insertion can be performed before or after column conversion. However, it is necessary to insert stuffy bits for each column before column conversion, and it is more convenient to insert stuffy bits and perform speed conversion for framing at the same time. Create time slots for additional bits at equal intervals, or time slots for stuffy bits as necessary, and place various additional bits in the time slots for additional bits. Arrange them in a pattern, frame them, and then perform column conversion. The unit of repetition of the inserted various additional bits as a whole is called a frame.
The unit consisting of the first additional bit and the following information bit is called a subframe (before column conversion). Therefore, one frame before column conversion is composed of a plurality of subframes each consisting of a plurality of bits whose first bit is an additional bit.

The above signal processing is performed at the transmitting end of the wireless line, and the inverse conversion process of this signal processing is performed at the receiving end.

In conventional signal processing methods, the number of columns before and after column conversion is
Equal consideration was not given to the relationship between 6 and the subframe length or frame length. Therefore, the additional bits placed at specific positions in the frame before column conversion are not necessarily placed at one fixed position in the frame after column conversion, and furthermore, the intervals between them may not be constant.

For example, if the number of columns before and after column conversion is 5,2 and the frame length before column conversion is an odd number, the additional bit placed at the beginning of the first column frame before column conversion is
Two values alternately arranged in the first column and the second column and whose intervals differ by 2 appear alternately.

[Problem to be solved by the invention]

In the conventional signal processing method described above, after converting k columns into one column, specific additional bits are not necessarily arranged in the same column, and the intervals between them are not necessarily constant. It is extremely difficult to frame-synchronize and add additional bits to a single-column data signal received at an intermediate relay station. It is necessary to add and drop bits and then convert them into four columns again, which has the disadvantage that the intermediate relay station equipment becomes complicated and expensive.

An object of the present invention is to provide a signal processing method in which specific additional bits are arranged at equal intervals in the same column even after column conversion into one column, and additional bits can be easily added/dropped in four columns at an intermediate relay station. It's about doing.

[Means to solve the problem]

The signal processing method of the present invention is based on the k input from the carrier terminal equipment.
(k is a natural number) The data signal of the column is converted into a frame consisting of multiple subframes by converting the speed of each column at high speed and inserting additional bits at predetermined positions. In a signal processing method that converts the signal into a sequence (integer) and sends it to a wireless line, the length of the subframe is set to kJn (n is a natural number).

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is an explanatory diagram showing the frame structure before column conversion in an embodiment of the present invention, and FIG. 2 is an explanatory diagram showing the frame structure after column conversion.

In this embodiment, five columns of data signals are input from the carrier end station device at the sending end, and these five columns of data signals are processed and sent to a four-phase phase modulation wireless line. Therefore,
The number of columns before and after column conversion is 5.2.

Five columns of data signals inputted from the carrier terminal equipment are subjected to speed conversion at high speed for each column, and are framed into frames each consisting of 12 subframes.

Each framed data signal is sequentially named a data signal DI-D5 from the first column (see FIG. 1). In this example, the subframe length is ρn, n=1, and 5X
2X1=10. The first bit of each subframe is an additional bit, stuff bit, or information bit.
The 10th to 10th bits are information bits. The frame length is 10×12=120.

In Figure 1, the reference numerals written in the 12 boxes representing each subframe in one frame indicate the subframe (
represents an additional bit or stuff bit placed at the beginning of the For example, the stuffy bit Ai is placed in the last subframe of the frame of the data signal Di (i=1 to 5). However, depending on the speed of the first column data signal before speed conversion, the bit at the position of the stuffy bit Ai becomes a stuffy bit or an information bit. Five stuff control bits C11 to Cis indicating whether these bits are stuff bits or information bits are placed in the even numbered (not the last) subframe of the frame of the data signal Di. In the odd-numbered subframes of the frames of the data signals Di and D2, there are two systems of frame synchronization pins (F a + to F a s, F b +) each comprising a frame synchronization pattern of 6 bits.
'Place F b s. Data signal D3. The odd-numbered subframe of the D4 frame has two digital service channels (Digital 5 service channels).
Channel r DSC) bits Sea and SCb are placed. Further, a parity check pin (P) is arranged in the odd numbered subframe of the frame of the data signal D5.

FIG. 1 also shows the bit structure of each leading subframe of the data signals D1 to D5.

Each of the bits with reference numbers 1 to 45 in these subframes is an information bit.

The data signal D1~ is framed as shown in FIG.
When D5 is column-converted into two columns, the data signal Dl after column conversion is
The frame structure of 1 and D12 is as shown in FIG.

As can be seen by comparing and contrasting FIG. 1 and FIG. 2, additional bits arranged at equal intervals in the same column before column conversion are also arranged at equal intervals in the same column after column conversion.

That is, parity check pick) P, DSC pick) S
Each of Ca is arranged in the data signal Dll at a period of 50 bits, and the DSC pins and SCb are arranged at a period of 50 bits in the data signal D12. Stuff bit AI
The related stuff control pins) Ci+ to C1 are also arranged at the frame period and in the same column for each i. Frame synchronization bit Fa, ~Fa
,+! A frame synchronization pattern is formed at 50-bit intervals in the data signal Dll, and this pattern is repeated at a frame period. The frame synchronization bits Fb, .about.Fbs are also arranged in the same manner except that they are arranged in the data signal D12. Frame synchronization bit Fa, ~F a a, F
Since b l to F b s were arranged at the same timing in the first column and the second column before column conversion, they are arranged at the same timing after column conversion. DSC bit SCa.

The same applies to SCb. In the 5-column/2-column column conversion, two additional bits placed at the same timing positions in the odd-numbered column before the column conversion and the column immediately after it are placed at the same timing even after the column conversion.

The data signals Dll and D12 are transmitted via wireless lines. At the intermediate relay station of the wireless line, the data signal D is sent from the receiver.
I 1. DI 2 is obtained. Data signal Dll, D1
2, frame synchronization bits Fa1 to Fa6 of each system. Fb
1 to Fb are arranged at equal intervals and at the same timing in both systems, and the DSC bits SCa, S of each system
Cb is similarly arranged at equal intervals and at the same timing in both systems, so that the data signals Di1. Di
2 to frame synchronization bits Fa+~Fag, Fb+”
'Detect Fbg, frame synchronize, DSC bit SC
It is very easy to add and drop a, SCb.

Therefore, there is no need to perform column conversion of 2 columns/15 columns/2 columns at the intermediate relay station.

At the receiving end of the wireless line, the data signal D11°DI2
is converted into data signals D1 to D5, and sent to the carrier end station device at the receiving end.

An example has been described above for the case where the number of columns before and after column conversion is 5.2, and the subframe length kj2n is 5X2X1=10. However, when the number of columns after column conversion l is an integer of 2 or more, Similar effects can be obtained by using the present invention even when the number of columns k and the value n before column conversion are arbitrary natural numbers.

〔Effect of the invention〕

As explained above, the present invention inserts additional bits into a data signal input from a carrier terminal equipment, converts it into a frame, converts the number of columns, and sends it out to a wireless line. By setting the length to the product of the number of columns before column conversion, the number of columns after column conversion, and an arbitrary natural number, it is possible to ensure that specific additional bits are placed at equal intervals in the same column even after column conversion. Therefore, it becomes easy to add and drop additional bits at the intermediate relay station, and the intermediate relay station apparatus can be made simple and inexpensive.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram showing the frame structure before column conversion in an embodiment of the present invention, and FIG. 2 is an explanatory diagram showing the frame structure after column conversion. Ai...stuff bits Ci+~Ois...
... Stuff control bit, D, , D, , Di...
...Data signal, Fa, ~Fas, Fbl~Fb
s...Frame synchronization bit, P...Parity check bit, SCa. SCb...DSC bit.

Claims (1)

[Claims] The data signal of k columns (k is a natural number) inputted from the carrier terminal equipment is converted into a frame consisting of multiple subframes by rapidly converting the speed of each column and inserting additional bits at predetermined positions. 1. A signal processing method in which the length of the subframe is kln (n is a natural number) in a signal processing method in which the subframe is converted into a string (l is an integer of 2 or more different from k) and sent to a wireless line.