JPH01290030A - Picture memory device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention is applicable to time base collectors, frame synchronizers, and other image processing devices, as well as image memories used in VTRs (video tape recorders), television receivers, etc. The present invention relates to a device, and particularly to a so-called dual port type image memory device equipped with an input buffer means and an output buffer means.

[Summary of the invention]

The present invention includes an input buffer means to which a video signal is supplied;
In an image memory device that has a memory means and an output buffer means for outputting the memory means, and in which input/output between each buffer means and the memory means is controlled using a write transfer signal and a read transfer signal, write transfer is performed. Disturbance of the demodulated image is prevented by providing an overtaking detection circuit that detects overtaking based on the order of the signals and readout transfer signals and the coincidence of the write address and the readout address.

[Conventional technology]

As an image memory device, a frame memory has been proposed that includes an input/output buffer and stores one frame of image information. This image memory device is provided with a memory cell array in which cells are arranged in a 7-trix pattern, and one line of image data (for example, 960 days) is stored in each word direction.

By the way, there is an image memory device in which a plurality of buffers whose capacity is smaller than the number of image information equivalent to one line are provided as human output buffers, and data is transferred between the sofa and the memory cell array by switching between these buffers. For example, such an image memory device is disclosed in Japanese Patent Application Laid-Open No. 62-2563.
It is described in Publication No. 00. In such an image memory device, transfer between the input cover sofa and the memory cell array is controlled by a write transfer signal T? The transfer between the sofa and the memory cell array is controlled by the read transfer signal TR. That is, for each line, each transfer signal T is divided according to the number of divided buffers.

Pulses T and l are generated, and input/output transfer is performed at that timing. These transfer signals T, T□ are generated inside the memory device by a required clear signal, etc., and are not supplied as signals from the outside.

Some image memory devices are known in which writing and reading are performed in parallel to the memory cell array, and the write transfer signal T8 and read transfer signal TR are not synchronized. Each asynchronous transfer signal T. , T.R.
In an image memory device that generates a write transfer signal T
The period of 1 is longer than the period of the read transfer signal TR. Then, as shown in FIG. 6, each transfer signal T is asynchronous. , T.R.
In an image memory device that generates a signal, there are cases where the timings of the transfer signals T, A, and TR coincide with each other. The timing is indicated by time C in FIG.

When pulses T+, . . . TR are sent at the same time in this way, malfunctions generally occur in memory devices. Therefore,
In conventional image memory devices, an asynchronous write transfer signal T. The read transfer signal TR is shifted back and forth in time. In FIG. 6, the read transfer signal PRI at time Tc
An example is shown in which the read transfer signal PR2 is set earlier in time.

[Problems to be Solved by the Invention] By the way, when one of the transfer signals Tw and T* as described above is shifted in time, if the write and read addresses match, so-called "overtaking" occurs. arise.

FIG. 7 is an explanatory diagram at the time of "overtaking", in which the solid line indicates the change in write address over time,
The broken line shows the change in read address over time. The period of the write address is longer than the period of the read address, and in the read field N, the data of the write field n is read. However, in the write fee monthly rate n+], an overtaking path occurs at point Pa, and in the read field l'N+1 at time T1 after that point Pa, the data of field n, which is the previous field of writing, is is being read out. As a result, in the image signal transfer method in which the phase is inverted for each field, a hue error as shown in FIG. 8 occurs after "overtaking", and the demodulated image is disturbed.

As a technology for solving such problems, the applicant has previously proposed a related technology that uses status information in data to determine hue errors (Japanese Patent Laid-Open No. 63
(Refer to Publication No.-7594). However, the asynchronous transfer signal T11. Rather than a technology using TR, a configuration that separates the video signal and status information is required.

Therefore, the present invention deals with each transfer signal T. , T8, while preventing image distortion.

[Failure to solve the problem]

In order to achieve a series of objects, the image memory device of the present invention comprises an input buffer means to which a video signal is supplied, a memory means to which the output of the input buffer means is supplied under the control of a write transfer signal, and a read In an image memory device comprising output buffer means to which the output of the memory means is supplied under the control of a transfer signal, the write transfer signal and the read transfer signal are asynchronous, and either the write transfer signal or the read transfer signal is The present invention is characterized in that it includes overtaking detection means that generates a required overtaking detection signal when the write transfer address and the read transfer address match when one of the pulses is repeatedly issued.

In this invention, the structure of the memory means is DRAM.
, regardless of sRAM. In addition, the number of divisions of the large buffer means and the output huff 7 means is ■ or an integer of 2 or more,
It is not particularly limited. Each person may have a plurality of output buffer means. For example, an example of the input/output buffer means may be a SAM (serial access memory). The image memory device according to the present invention may be configured to allow random access as well as serial access.

Furthermore, when pulses of either the write transfer signal or the read transfer signal are repeatedly issued, two or more pulses of the read transfer signal are generated in the time between any pulse of the write transfer signal and the next pulse. This refers to a case where two or more pulses of a write transfer signal occur consecutively in the time between an arbitrary pulse of a read transfer signal and the next pulse.

[Effect]

In a memory where the write transfer signal and the read transfer signal are asynchronous, 'overtaking' occurs when the pulses of one of the transfer signals are emitted in succession and the write transfer address and the read transfer address match. Therefore, by providing an overtaking detection means to detect these,
Overtaking detection is performed effectively.

〔Example〕

Preferred embodiments of the present invention will be described with reference to the drawings.

As shown in FIG. 1, the image memory device of this embodiment has an input buffer 11. Memory cell array 12.
It is composed of an output buffer 13 and a controller circuit 14, and an overtaking detection circuit 1 surrounded by a broken line in the figure is connected to the memory main body.

First, the video input signal DIN, which is serial data, is input to the input buffer 11 of the memory main body, which is converted into parallel data and output to the memory cell array 12. This input buffer 11 is composed of, for example, two SAMs (serial access memories). For example, a write transfer signal T having N2 pulses for each line.
Each SAM is switched by w, and the data of N1 dots is sequentially sent to the memory cell array 12.

In the above memory cell array]2, one line has data of N1 (for example, 60) x N2 (for example, 16) dots,
This is a DRAM having a required number of lines (for example, 306 lines). Control such as line selection is performed by the controller circuit 14.

The output buffer 13 of the memory main body is connected to the memory cell array 1
It receives the parallel output data from 2, and outputs the output signal while switching between the two SAMs. Output serially as LIT. The signals used to switch between these two SAMs are read transfer signals T and l.

The controller circuit 14 of the memory main body is supplied with necessary clear signals and the like, and controls the memory cell array 12. This controller circuit 14 receives the write transfer signal T. In addition, the read transfer signal T is formed. And each of these transfer signals T. , TR are used for transfer control and are simultaneously output to an overtaking detection circuit 1 for detecting overtaking.

The overtaking detection circuit 1 includes a write transfer address counter circuit 2, a read transfer address counter circuit 3, an address-number construction circuit 4, and an order determination circuit 5.
and an AND circuit 6. This overtaking detection circuit 1 can be installed inside or outside the chip.

The write transfer address counter circuit 2 receives the write transfer signals T and A, and counts write transfer addresses. The write transfer address to be counted consists of a vertical address and a horizontal address such as AD or (v,h).

Similarly, the read transfer address counter circuit 3 receives the read transfer signal TR and receives the read transfer address A.
DR is counted. The counted read transfer address ADR is also the write transfer address A D 1
1, it consists of a vertical address and a horizontal address such as (v, h).

The address-number configuration circuit 4 inputs the write transfer address AD11 of the write transfer address counter circuit 2 and the read transfer address ADR of the read transfer address counter circuit 3, compares them, and if they match. Then, set the output to "H" level. When they do not match, the output is set to "L" level.

The order determining circuit 5 receives each of the transfer signals T and TR and determines the order of pulses of each of the transfer signals T and TR. In the write transfer signal Tu and the read transfer signal TR, the pulses are generated alternately in normal times when there is no overtaking, but when the transfer pulses are controlled to avoid overlapping of each pulse, the order becomes out of order, and the pulses are generated alternately. A series of pulses are emitted. Therefore, during the time between any pulse of the write transfer signal T8 and the next pulse, the read transfer signal T□
two or more pulses occur in succession, or
The write transfer signal T is determined to be asynchronous by detecting when two or more pulses of the write transfer signal TW occur consecutively in the time between an arbitrary pulse of the read transfer signal TR and the next pulse. If so, an operation that shifts the read transfer signal TR forward or backward in time is determined.

The outputs from the address-number construction circuit 4 and the order determining circuit 5 are respectively input to the two-note AND circuit 6. “
Overtaking°” is the transfer signal T, T+t as described above.
This occurs when one of the above occurs repeatedly, and the write transfer address AD and the read transfer address AD are the same address. Therefore, when the outputs of the address-number configuration circuit 4 and the order determining circuit 5 are at the H'' level,
Assuming that overtaking has occurred, an H'' level output is generated.

FIG. 2 shows the image memory device of this embodiment connected to the chroma inverter 22, and the memory main body 2
1 is outputted via a chroma inverter 22, and the chroma inverter 22 controls the phase according to the field according to the output signal from the overtaking detection circuit 1 at the time of overtaking. Therefore, the demodulated signal from the image memory device of this embodiment is free from image disturbances such as hue shift.

FIG. 3 is a time chart of each transfer signal T11.TR and each transfer address AD, AD, l at the time of overtaking.When the pulse of the write transfer signal TI, l is input at time L1, the write transfer signal T11. The address of the counter circuit 2 advances by one, and its write transfer address ADl,... changes from (h, v-1) to (h.

■). Next, at time t2, a pulse of the read transfer signal TR is input, the address of the read transfer address counter circuit 3 advances by one, and the read transfer address A
DR becomes (h, v) from (h, v-1). Then, at this time, the write transfer address AD and the read transfer address AD.

The addresses in [A] above will match each other.
The address match detection circuit 4 outputs an "H" level output.

After the pulse of the read transfer signal TR is generated, the write transfer signal T is normally generated. is output from the memory main body, but when overtaking, the same pulse of the read transfer signal TR is emitted repeatedly (time t3). When pulses of one of the transfer signals are emitted repeatedly, the order determining circuit 5
The output of is ``H'' level. Then, in the AND circuit 6, both of the two input signals become ``14 level level'', and a signal indicating that overtaking has occurred is outputted.

The output signal is then supplied to the Romaine Hearter 22 as shown in FIG. 2, thereby preventing image distortion.

Next, another example of the overtaking detection circuit in the image memory device of this embodiment will be described with reference to FIGS. 4 and 5.

As shown in FIG. 4, this overtaking detection circuit includes a pair of counter circuits 41.45 and latch circuits 42.43.4.
4, 46, 47.48, and a pair of coincidence detection circuits 49.5
0 and an OR circuit 51.

Write transfer signal T. inputs a clock to the counter circuit 41 and latch circuits 42, 47, and 48. Further, the read transfer signal T is clocked into the counter circuit 45 and latch circuits 46, 43, and 44.

The output signal A of the counter circuit 41 is output from the latch circuit 42.
43. The output signal A2 of the latch circuit 42 is
- supplied to the number output circuit 50;

The output signal A3 of the latch circuit 43 is supplied to the - number construction circuit 49 and also to the latch circuit 44. Output signal A4 of latch circuit 44 is supplied to coincidence detection circuit 49. Further, the output signal B1 of the counter circuit 45 is supplied to latch circuits 46 and 47. The output signal B2 of the latch circuit 46 is supplied to the minus number output circuit 49. The output signal B3 of the latch circuit 47 is supplied to the -number output circuit 50 and also to the latch circuit 48. Output signal B4 of latch circuit 48 is supplied to coincidence detection circuit 50.

And each output signal P of the above-mentioned - number construction circuit 49.50,
Q is supplied to an OR circuit 51, and the output of this OR circuit 51 is used as the output of the overtaking detection circuit. That is,
As shown in FIG. 2, for example, the chromine inverter 22
control.

Next, the operation of this overtaking detection circuit will be explained with reference to FIG. Note that the output signals A, ~A4 apply to the data on the write transfer address ADl, l side, and the output signals 81 to B4 apply to the data on the read transfer address AD, side.

First, from time tlG to time t11, normal operation without "overtaking" is performed. At time t1, a pulse of the write transfer signal T9 is input, and the counter circuit 41
Then, the value of the write transfer address AD advances by one. At the same time, the latch circuit 42 latches the output signal AI. That is, the output signal A2 of the latch circuit 42 becomes a signal of the counter circuit 41 one clock earlier. Furthermore, at this time tlO, the latch circuits 47 and 48 also operate. The latch circuits 47 and 48 latch the read transfer address ADR at the pulse timing of the write transfer signal T1. The latch circuit 48 uses the output signal B3 of the latch circuit 47 one clock earlier as the output signal B4.

At time tl+, the above operation occurs in the system on the read transfer signal T8 side. That is, in the counter circuit 45, the value of the read transfer ADR advances by one, and the output signal B2 of the latch circuit 46 becomes a signal one clock before the output signal B1 of the counter circuit 45. Further, the latch circuits 43 and 44 latch the write transfer address AD at the timing of the pulse of the read transfer signal T. The latch circuit 44 uses the output signal A3 of the latch circuit 43 one clock earlier as the output signal A4.

Time 1. The output signal A1 of the counter circuit 41 is formed by □ (
v, h). At this time, the latch circuit 42
The output signal A2 of is (v, h-1) one clock ago, and the output signals B:l, B4 of the latch circuits 47 and 48 which latch the read transfer address ADR are as follows.
(v, h-1) and (v, h-2), respectively.

Next, the time is also 3, and the output signal B1 of the counter circuit 45
Suppose that becomes (v, h). This means that the write transfer address AD and the read transfer address AD match. At this time, latch circuit 4
The output signal B2 of 6 is (v.

h-1), and the respective output signals A of the latch circuits 43 and 44 which latch the write transfer address AD, 1.
3. A4 has already output signal A, (v.

h), so (v, h) and (v.

h-1).

Then, when overtaking occurs, the same transfer pulse is repeatedly issued. That is, at time t13, a pulse of the read transfer signal TR is generated, and another pulse of the read transfer signal TR is generated (time t14). Then, first, the output signal B+ of the counter circuit 45 becomes (v,
h+1), and the output signal B2 of the latch circuit 46 delayed by one clock becomes (v, h). This output signal B2
is input to the matching circuit 49 which refers to the read transfer address ADR. At the pulse of the readout transfer signal T8 at time t11, the launch circuit 43 that inputs the clock
．． 44 also works. However, the output signal A1 of the counter circuit 43, which is the input signal of the latch circuit 43, has no data change because there is no clock input after time t1□. Therefore, even if the latch circuit 43 operates at time t14, the same (v, h) as the previous clock (v, h) is simply latched again, and the output signal A3 of the latch circuit 43 is (v , h) remains. On the other hand, in the latch circuit 44, the data of (v, h) one clock ago becomes the output signal A4. Therefore, from the series of pulses at time t14, the output signals A3 and A4 of the latch circuits 43 and 44 match.

Here, the signal A input to the coincidence circuit 49 after time tz
3. A, , B2 all match as (v, h). Signal A3. The fact that not only A4 but also the output signal B2 match means that even the read transfer address ADR matches the write transfer address ADl, . Due to this coincidence, the output P of the minus number circuit 49 becomes the "H" level, which means overtaking, and is outputted via the OR circuit 51. Then, the disturbance in the image will be corrected.

Hereinafter, time L151 time t16. . . . pulses are input to the overtaking detection circuit one after another, but because the pulses are repeated and the addresses do not match, the OR circuit 51 does not become "H parehel".

Note that when the write transfer transmission M'Tw pulses are issued repeatedly, the latch circuit 41.4
8 output signal B3. The data at the address B4 match, and furthermore, the data at the read transfer address ADR at this time is supplied from the latch circuit 42. Then, the minus number circuit 50 judges whether or not they match, and if they match, that is, when overtaking, the output signal Q is ``H''''.
Therefore, the OR circuit 51 outputs the required output.

In this way, in the overtaking detection circuit shown in FIG. 4, in the circuit configuration for detecting address coincidence, the timing of the pulse of the read transfer signal T is used as a clock on the write transfer address AD11 side, and the timing of the pulse of the read transfer signal T is used as a clock. On the address ADR side, the pulse timing of the write transfer signal T11 is used as a clock. Therefore, when a series of one pulse occurs, it will be detected by the coincidence circuits 49, 50 in the form of address coincidence, and "overtaking" will be definitely detected.

Note that the image memory device of the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the gist thereof.

[Effects of the Invention] The image memory device of the present invention is provided with overtaking detection means that operates in response to pulses of each transfer signal. Therefore, overtaking detection is used to prevent image disturbance.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of an image memory device of the present invention, and FIG. 2 is a block diagram for explaining an example of its application.
FIG. 3 is a time chart for explaining the overtaking operation, FIG. 4 is a circuit diagram showing another example of the overtaking detection circuit according to the image memory device of the present invention, and FIG. 5 is the overtaking operation shown in FIG. Figure 6 is a time chart to explain the operation of the detection circuit, Figure 6 is a time chart 1 to explain each transfer signal, Figure 7 is an explanatory diagram to explain overtaking, and Figure 8 is a time chart at the time of a hue error. FIG. 3 is a schematic diagram for explaining a screen. 1... Overtaking detection circuit 2... Write transfer address counter circuit 3... Read transfer address counter circuit 4... Address-number configuration circuit 5... Sequence detection circuit Patent applicant Sony Corporation agent Patent attorney Akira Koike (and 2 others) I! l! :I! Mi ((2 items). 5. α Figure 8-2071

Claims (1)

[Scope of Claims] An input buffer means to which a video signal is supplied, a memory means to which an output of the input buffer means is supplied under control of a write transfer signal, and an output of the memory means is supplied under control of a read transfer signal. In the image memory device, the write transfer signal and the read transfer signal are asynchronous, and when pulses of either the write transfer signal or the read transfer signal are successively emitted, the write transfer signal and the read transfer signal are An image memory device comprising overtaking detection means for generating a required overtaking detection signal when a transfer address and a read transfer address match.