JPH01291464A - Mis field-effect semiconductor device - Google Patents

Abstract

PURPOSE:To maintain a resistance value small as a whole, and to improve a conductance by providing a conductive film having a low resistance value from the diffused region, bringing it into contact with the surface of an impurity diffused region and interposing its end between the diffused region and an interlayer insulating film. CONSTITUTION:A conductive film 9A exists on the surfaces of an n<+> type source region 12 and an n<+> type drain region 13, the end of the film 9A is intruded into an interlayer insulating film 8 to reach the vicinity of a gate electrode 3. The end of the film 9A and the electrode 3 are so isolated through an interlayer insulating film 5 having a predetermined thickness that the film 9A and the electrode 3 are not affected by the influence of an electric field. Since the film 9A exists in the interlayer insulating film for collecting hot carriers, the input carrier flows out as part of the drain current through the film 9A. Accordingly, it prevents hot carrier effect from occurring. Even if the resistance value of an impurity diffused region for forming a LDD structure is large, it is sufficiently reduced by the presence of the film 9A, thereby improving the conductance of a MIS field effect transistor.

Description

[Detailed Description of the Invention] [Summary] Regarding a small-sized Mis field effect semiconductor device that is effective for use in memory and logic that require high integration or high speed, a state in which carriers are captured by the glabella insulating film covering the gate electrode This method prevents the occurrence of the ho-nod carrier effect and lowers the resistance value in the impurity diffusion region forming the LDD structure, thereby producing a MIS field-effect semiconductor device that always has high conductance. A gate electrode formed on a semiconductor substrate with a gate insulating film interposed therebetween and whose side surfaces are covered with an interlayer insulating film, and a gate electrode formed on the surface of the semiconductor substrate with a channel side tip below the interlayer insulating film. an impurity diffusion region having a conductivity type opposite to that of the semiconductor substrate; and a conductive film having a value.

[Industrial application field]

The present invention relates to a compact MIS field effect semiconductor device that is effective for use in memory and logic that require high integration or high speed.

Currently, with the increasing integration of semiconductor devices, the miniaturization of MIS field effect transistors has progressed, and the gate length has become 0.7 [μm].
] and is expected to become even shorter in the future. However, even if the gate length is shortened in this way, the standard power supply voltage is still 5 [V], so the electric field between the source and drain becomes strong, and there is a possibility that the withstand voltage cannot be maintained.

LDD (l i
However, there is a problem in that a large conductance cannot be obtained due to the high resistance value of the impurity diffusion region, and the electric field strength in the channel region becomes high. As a result, hot carrier effects become significant and conductance decreases during operation.

Therefore, it is desired to develop a MIS field effect semiconductor device having high resistance to hot carriers and large conductance.

[Prior Art] FIG. 14 shows a cutaway side view of a main part of a Mis field effect transistor having a normal LDD structure.

In the figure, 21 is a p-type silicon semiconductor substrate, 22 is a field insulating film made of silicon dioxide (SiOz), and 2 is a p-type silicon semiconductor substrate.
3 is a gate insulating film made of silicon dioxide, 24 is a gate electrode made of polycrystalline silicon, 25 is a mask/interlayer insulating film made of silicon dioxide, 26 is an n-type source region, 27 is an n-type drain region, and 28 is a gate insulating film made of silicon dioxide. 29 is an interlayer insulating film called a side wall, 30 is an n++ source region, 31 is an n+ type drain region 32 is made of phosphosilicate glass ( pho 5phosil
33 is a source electrode made of aluminum,
Reference numeral 34 indicates a drain electrode made of aluminum, and reference numeral 35 indicates a gate electrode made of aluminum.

In general, the LDD structure is particularly effective when applied to the drain region, and by forming a low impurity concentration region on the channel region side as shown in the figure and suppressing the spread of the depletion layer into the channel region, the LDD structure can be applied to the source region. The aim is to prevent punch-through current from flowing between the drain and the drain, and to improve the withstand voltage.
] It is possible to maintain sufficient source-drain breakdown voltage against the power supply voltage.

[Problem to be solved by the invention]

In the Mis field effect semiconductor device having the LDD structure, during operation, hot carriers are generated in the vicinity of the drain side low impurity concentration region, that is, the n-type drain region 27, and a part of the hot carriers are generated in the interlayer insulating film which is the side wall. Incorporated into 29. The carriers thus captured in the glabellar insulating film 29 work to weaken the electric field from the gate electrode 24 and increase the resistance value of the n-type drain region 27, resulting in a hot carrier effect, that is, conductance during operation. A problem arises in that the value decreases.

In addition, the width of the low impurity concentration region (in the channel length direction) forming the same<LDD structure, that is, the width of the n-type drain region 27, etc., needs to maintain a sufficiently high source-drain breakdown voltage. There is a limit to how short it can be. Therefore, even if the gate length is miniaturized, the n-type drain region 27 etc. cannot be shortened arbitrarily, and its resistance value is high, which may cause the conductance to decrease. There are also drawbacks.

The present invention prevents the generation of hot carrier effects by preventing the glabella insulating film covering the gate electrode from maintaining a state of capturing carriers, and reduces the resistance value in the impurity diffusion region forming the LDD structure. An attempt is made to obtain a Mis field effect semiconductor device that always has high conductance by lowering the conductance.

[Means to solve the problem]

1 and 2 are cross-sectional side views of essential parts of a MIS field effect semiconductor device at key points in the process for explaining the present invention in detail.

In the figure, ■ is a p-type silicon semiconductor substrate, 2 is a gate insulating film made of silicon dioxide, 3 is a gate electrode made of polycrystalline silicon, 4 is a mask and interlayer insulating film made of silicon dioxide, and 5 is made of silicon dioxide. 6 is an n-type source region, 7 is an n-type drain region, 8 is a glabella insulating film that is a side wall made of silicon dioxide, 9A is a list of titanium silicide, etc. electrical film, 12 is n++ source region, 1
3 indicates an n+ type drain region.

FIG. 1 shows a Mis field effect semiconductor device having a structure almost the same as the conventional LDD structure, except that the n++
A conductive film 9A exists on the surfaces of the source region 12 and the n+ type drain region 13, and the tip of the conductive film 9A penetrates into the interlayer insulating film 8 and reaches the vicinity of the gate electrode 3. However, the tip of the conductive film 9A and the gate electrode 3 are connected via an interlayer insulating film 5 having a predetermined thickness so that the conductive film 9A and the gate electrode 3 are not affected by the electric field. They are separated by

In FIG. 2, only the n-type source region 6 and n-type drain region 7, which are the source region and drain region with a low impurity concentration in the conventional LDD structure, are present, and the source region and the drain region with a high impurity concentration are present. The part corresponding to is the conductive film 9
The list depends on A.

In either of the MIS field effect semiconductor devices shown in FIG. 1 or 2, the conductive film 9A is interposed in the interlayer insulating film that captures hot carriers, so the captured carriers are transferred to the conductive film. 9A as a part of the drain current. Therefore, the hot carrier effect is prevented from occurring, and even if the resistance value of the impurity diffusion region forming the LDD structure is high, the conductive film 9A Therefore, the conductance of the Mis field effect transistor is improved.

For this reason, in the MIS field effect semiconductor device according to the present invention, a gate insulating film (e.g., gate insulating film 2) is formed on a semiconductor substrate (for example, a p-type silicon semiconductor substrate l) through a gate insulating film (e.g., gate insulating film 2). a gate electrode (e.g., gate electrode 3) whose side surfaces are covered with an interlayer insulating film (e.g., glabellar insulating film 8 or 11); An impurity diffusion region having a conductivity type opposite to that of the semiconductor substrate (for example, an n-
type drain region 7 or n-type source region 6) and the surface of the impurity diffusion region, the tip thereof is interposed between the impurity diffusion region and the interlayer insulating film, and has a lower resistance value than the impurity diffusion region. A conductive film (for example, a conductive film 9A made of titanium silicide) is provided.

[Effect]

By adopting the above method, even if hot carriers generated near the channel side of the drain region are taken into the interlayer insulating film, the hot carriers will flow away as part of the drain current through the conductive film. , the hot carrier effect, that is, the problem of reduced conductance during operation, is solved, and although the same structure as the low impurity concentration region in the LDD structure is used, the presence of the conductive film reduces the overall Since the resistance value can be maintained low, the conductance is improved.

〔Example〕

Figures 3 to 13 are cross-sectional side views of essential parts of the Mrs field effect semiconductor device at key points in the process for explaining the manufacturing of an embodiment of the present invention, and these figures will be referred to below. I will explain as I go along.

See Figure 3 (11) By applying a selective thermal oxidation method using, for example, a silicon nitride (Si3N4) film as an oxidation-resistant mask, a field insulating film made of silicon dioxide (not shown) is applied to a p-type silicon semiconductor substrate l. form).

(2) The active region of the p-type silicon semiconductor substrate 1 is exposed by removing the silicon nitride film and the like.

(3) By applying a thermal oxidation method, the thickness can be reduced to approximately 1
A gate insulating film 2 made of silicon dioxide is formed in an amount of about 00 to 200 people.

(4) Chemical vapor deposition (chemica 1 vap).

r deposition: by applying the CVD method, the thickness can be adjusted, for example, from 3000 to 4000.
A polycrystalline silicon film of about the size of a person is grown.

This polycrystalline silicon film may contain impurities in advance and may be grown, or impurity ions may be implanted at the stage of growth.

(51 By applying the CVD method, the thickness may be approximately 1
A mask-cum-interlayer insulating film 4 made of silicon dioxide is grown in an amount of about 000 (people) to 2,000 (people).

(6) Pattern the mask/interlayer insulating film 4 into a gate electrode and other electrode/wiring patterns by applying normal photolithography technology, and then use this as a mask to pattern the polycrystalline silicon film and gate insulating film 2.
Perform patterning. Note that the patterned polycrystalline silicon film is used as the gate electrode 3.

See FIG. 4 (7) By applying a thermal oxidation method, the surface of the p-type silicon semiconductor substrate 1 and the side surfaces of the gate electrode 3 are covered with a surface protection and interlayer made of silicon dioxide having a thickness of, for example, about 150 mm. An insulating film 5 is formed. Note that this surface protection/interlayer insulating film 5 has a slight influence on the thickness of the interlayer insulating film 4, but is omitted for the sake of brevity.

(8) As ions are implanted by applying an ion implantation method.

The dose in this case is, for example, approximately 1×l O13
(cm-") to l x l O12 (cm-"), and it is also possible to use an appropriate n-type impurity ion in addition to As ions, or if the silicon semiconductor substrate 1 is If it is a type, it is optional to use an n-type impurity such as boron ions.

See Figure 5. (9) In order to activate the impurities ion-implanted in step (8), PTA (Rapid T
by applying a herbal annealing method at a temperature of, e.g., about 1000°C and a time of, e.
Heat treatment is performed for [seconds] to form an n-type source region 6 and an n-type drain region 7 that can actually operate.

By applying the OICVD method, see FIG.
An interlayer insulating film 8 made of silicon dioxide with a thickness of about 0.00 to 1500 C. is grown.

Refer to Figure 7 0υ Reactive ion etching using a mixed gas of trifluoromethane and carbon tetrafluoride (CHF3+CF) as the etching gas.
The interlayer insulating film 8 is formed by applying the ng:RIE) method.
Perform anisotropic etching.

As a result, the interlayer insulating film 8 and the surface protection/interlayer insulating film 5 have a so-called side wall shape in which only the portions attached to the side surfaces of the gate electrode 3 made of polycrystalline silicon remain.

Refer to FIG. 8 α. A titanium (Ti) film 9 having a thickness of, for example, about 500 mm is formed by applying, for example, a sputtering method. The thickness of the titanium film 9 is approximately 300 [people] to 800 [people].
You may choose within the range of [people].

Refer to Figure 9. α By applying the PTA method, the temperature can be reduced to about 6
The heat treatment is performed at a temperature of about 20° C. for a time of, for example, about 60 seconds.

In this way, the titanium film 9 and a part of the p-type silicon semiconductor substrate 1 react and are converted into a conductive film 9A made of titanium silicide, and under the above conditions, the thickness thereof is, for example, about 1
000 C people].

Refer to FIG. 10. By immersing the titanium film 9 in 041 N H40H/Hz Oz, the titanium film 9 that was unreacted in the heat treatment in step 0 is removed.

See Figure 1109 By applying the CVD method, the thickness can be reduced, for example, by approx.
An interlayer insulating film 11 made of silicon dioxide is grown to a thickness of about 000 (people) to 20'OOC people.

See Figure 12 0ω RI with CHF3+CF4 etching gas
The interlayer insulating film 11 is anisotropically etched by applying the E method.

As a result, the glabellar insulating film 11 also takes on the shape of a so-called side wall, and the tip of the conductive film 9A made of titanium silicide is embedded therein.

Refer to FIG. 13. As ions are implanted by applying the aη ion implantation method.

In this case, the dose amount is, for example, approximately 1×10+4(
cm-") ~ I x 10I5 (cm-") If so, as described above, a p-type impurity such as boron ions is used.

α (To) In order to activate the impurities ion-implanted in the step αη, heat treatment is performed at a temperature of, for example, about 1000 ['C] and a time of, for example, about 10 [seconds] by applying the RTA method, Actual operable n++ source region 12
In addition, an n+ type drain region 13 is formed.

Alpha mark After this, the product is completed through the usual processes such as forming the glabella insulating film and cover film, forming the electrode contact window, and forming the electrodes and wiring.

In the embodiments described above, the heat treatment using the RTA method can be replaced by annealing using a furnace.

N-type source region 6 and n-type drain region 7 in the MIS field effect semiconductor device manufactured as described above
It is natural from the dose that these correspond to the source and drain regions with low impurity concentration in the LDD structure, and furthermore, the tip of the titanium silicide film that is in contact with it corresponds to the glabellar insulation that forms the side wall. membrane 11
It has a structure that makes it easy to collect hot carriers that are embedded in and captured there.

Further, the lateral expansion of the conductive film 9A made of titanium silicide is very small, and is about 500 [people] in the above embodiment.

Furthermore, the sheet resistance value of the titanium silicide conductive film 9A is about 2 [Ω/hole].

In the above step, the surface protection/interlayer insulating film 5 is formed slightly thicker, and then the n-type source region 6, the n-type drain region 7, and the conductive film 9A made of titanium silicide are formed.
After that, an interlayer insulating film 8 which is a side wall is formed, and then an interlayer insulating film 11 and an n+
If the formation of the + source region 12 and the n + -type drain region 13 is omitted, a MIS field effect semiconductor device having the structure described with reference to FIG. 2 can be obtained, and this structure also operates satisfactorily as an LDD structure.

In the above embodiment, titanium silicide was used as the material for the conductive film formed on the drain region and the source region, but the material is not limited to this, and for example, tungsten silicide can be used.
Silicide (WSix) and molybdenum silicide (M
oSi2), and tungsten nitride (WN
), molybdenum nitride (MoN), etc.

〔Effect of the invention〕

In the MIS field effect semiconductor device according to the present invention, there is provided an impurity diffusion region whose channel side tip is located below the glabella insulating film covering the side surface of the gate electrode and whose conductivity type is opposite to that of the semiconductor substrate, and the impurity diffusion region. A conductive film is provided which is in contact with the surface and whose tip is interposed between the impurity diffusion region and the interlayer insulating film and whose resistance value is lower than that of the impurity diffusion region.

By adopting the above structure, even if hot carriers generated near the channel side of the drain region are taken into the glabellar insulating film, the hot carriers will flow away as part of the drain current through the conductive film. , the hot carrier effect, that is, the problem of reduced conductance during operation, is solved, and although the same structure as the low impurity concentration region in the LDD structure is used, the presence of the conductive film reduces the overall Since the resistance value can be maintained low, the conductance is improved.

[Brief explanation of the drawing]

1 and 2 are cross-sectional side views of essential parts of a Mis field effect semiconductor device at important process points for detailed explanation of the present invention, and FIGS. 3 to 13 are manufactured embodiments of the present invention. FIG. 14 is a cross-sectional side view of a main part of a Mis field effect semiconductor device at a key point in the process for explaining a case in which a conventional example is used. In the figure, 1 is a p-type silicon semiconductor substrate, 2 is a gate insulating film, 3 is a gate electrode, 4 is a mask/interlayer insulating film, and 5 is a p-type silicon semiconductor substrate.
6 is a surface protection/interlayer insulating film, 6 is an n-type source region, 7 is an n''' type drain region, 8 is a glabella insulating film (side wall), 9 is a titanium film, and 9A is a conductive film made of titanium silicide. , 11 is an interlayer insulating film (side wall),
Reference numeral 12 indicates an n++ source region, and reference numeral 13 indicates an n+ type drain region. Patent Applicant: Fujitsu Ltd. Representative Patent Attorney Shoji Aitani Representative Patent Attorney Hiroshi Watanabe - Figure 13 Figure 14

Claims (1)

[Claims] A gate electrode formed on a semiconductor substrate with a gate insulating film interposed therebetween and whose side surfaces are covered with an interlayer insulating film, and a gate electrode formed on the surface of the semiconductor substrate with a channel side tip below the interlayer insulating film. an impurity diffusion region having a conductivity type opposite to that of the semiconductor substrate; and an impurity diffusion region that is in contact with the surface of the impurity diffusion region and whose tip is interposed between the impurity diffusion region and the interlayer insulating film and has a resistance value lower than that of the impurity diffusion region. A MIS field effect semiconductor device comprising a conductive film.