JPH0964363A - MOS semiconductor device and method of manufacturing the same - Google Patents

Abstract

(57) Abstract: A semiconductor device and a semiconductor device in which, in the deep submicron region or less, the drain current does not decrease when the source / drain contacts are made single to narrow the width of the source / drain. A manufacturing method is provided. A source / drain resistance in a gate width direction when the number of source / drain contacts is reduced to one due to a thin silicide layer 8a in a shallow source / drain diffusion layer 6 and a deep source / drain diffusion layer 7. Can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS type semiconductor device and a method for manufacturing a MOS type semiconductor device. Especially,
The present invention relates to a MOS semiconductor device having a structure suitable for achieving a higher packing density and capable of operating at high speed with low power consumption, and a method for manufacturing a MOS semiconductor device.

[0002]

2. Description of the Related Art In order to improve the degree of integration of a large scale integrated circuit (so-called VLSI), miniaturization of a MOS type semiconductor device is an important issue.

With the miniaturization, the following two problems have become apparent.

(1) Due to the increase in parasitic resistance and parasitic capacitance, improvement in circuit characteristics according to the scaling law cannot be expected. Specifically, a) decrease in gate length and increase in RC delay effect of gate electrode by thinning gate insulating film b) increase in substrate concentration (Vt control, punch through stopper, channel stopper) drain per unit area Phenomena such as increase in junction capacitance are becoming problems.

(2) The gate electrode is designed to have a minimum size according to the scaling rule. However, contact (CW) between the source / drain diffusion layer arranged around the gate electrode and the first aluminum wiring layer (AL)
Requires a considerably large process margin for the gate electrode and the element isolation region. For this reason,
Even if the size of the gate electrode is reduced according to the scaling law, the area of the source / drain diffusion layer itself cannot be reduced so much. As a result, the area of the transistor as a whole becomes larger than the area determined by the scaling law, which prevents realization of high integration. Further, the increase of the area of the source / drain diffusion layer promotes the increase of the junction capacitance as shown in (1) b) above.

In order to solve these two problems,
Salicide processes have been proposed (eg IEEE Tra
ns. on ED, ED-29, 1982, pp531-535.).

FIG. 7 shows a cross section of a conventional transistor (salicide transistor) manufactured by using a salicide process. Here, 1 is a P-type semiconductor substrate, 2 is trench isolation, 3 is a gate insulating film, 4 is a gate electrode, 5
Is a SiO ₂ sidewall, 6 is a shallow N type diffusion layer, 7 is a deep N type diffusion layer, and 8 is a silicide layer.

A CM whose design rule is, for example, 0.5 μm
According to the OS process, the sheet resistance of the gate electrode is changed from 40Ω / □ to 2Ω / □ and the sheet resistance of the source / drain diffusion layer is changed from 100Ω / □ to 2 by silicidation.
Ω / □ Since the resistance of the gate electrode is small, the RC delay component of the gate electrode is very small.
Estimating the effect simply, for example, if the gate width is 10 μm
, The RC delay is about 8.5 ps to about 0.4 p.
s. Here, as the main parameters of the device, the gate length is 0.5 μm, and the gate oxide film thickness is 10 n.
m, the shallow source / drain diffusion layer and the deep source / drain diffusion layer have junction depths of about 150 nm and about 2, respectively.
00 nm and the impurity concentration on the surface is 6.
It is set to 0 × 10 ¹⁸ cm ⁻³ and 2.0 × 10 ²⁰ cm ⁻³ . The width of the sidewall is about 150 nm, and the thickness of the Ti layer for the silicide layer is 40 nm. The finally formed silicide layer has a thickness of 80 nm.

In the present specification, "junction depth"
Means that the impurity concentration is 1.0 × 10 ¹⁷ c from the Si substrate surface.
It is defined by the distance to the position where it becomes m ^-3 .

A major feature of the salicide process is shown in FIG.
That is, the layout as shown in (b) can be adopted. Here, in FIGS. 8A and 8B, 101 a, 1
01b indicates a region (active region) where the source / drain diffusion layer is formed, 102 indicates a region where a gate electrode is formed, and 103a and 103b indicate contact regions between the source / drain diffusion layer and the first AL wiring layer. Shown, 104a
Reference numerals 104b and 104b indicate regions where the first aluminum wiring is formed. By forming the silicide layer, the source /
Since the resistance of the drain region is greatly reduced, the source /
The number of contact regions provided in each of the drain regions can be reduced to one. In this way, since the area of the source / drain region can be reduced, high integration is achieved,
The drain junction capacitance can be reduced. At this time, if the width of the narrow active region (the distance from the end of the active region along the channel length direction to the end of the gate electrode) is 0.75 μm, the width of the silicide layer (from the end of the active region along the channel length direction) The distance to the edge of the sidewall) is 0.6 μm.
Therefore, for example, when the width of the gate electrode is 10 μm, the resistance of the source / drain region in the gate width direction is about 3 μm.
It becomes 0Ω. On the other hand, the channel resistance of the transistor is about 1
Since it is kΩ, the resistance of the source / drain region is sufficiently smaller than the channel resistance.

In the structure without silicidation shown in FIG. 8A, the layout of the first AL wiring is limited,
In the silicidized structure shown in FIG.
The degree of freedom in designing the layout of the AL wiring layer is improved.

[0012]

However, in the conventional structure, the size of M is in the deep submicron region.
This is insufficient for OS type semiconductor devices. For example, according to a CMOS process having a design rule of 0.13 μm, the width of the silicide located on the source / drain regions is designed to be about 0.08 μm. The width of the source / drain region is reduced to about 0.2 μm, while the width of the sidewall is 1 to suppress the short channel effect.
This is because scaling is not so great as about 20 nm. As an example of this case, the junction depth of the shallow source / drain diffusion layer is about 80 nm, and the impurity concentration on the surface is 1.0 × 10 ²⁰ cm ⁻³ . The junction depth of the deep source / drain diffusion layer is about 120 nm, and the impurity concentration on the surface is 2.0 × 10 ²⁰ cm ^−3.
Becomes The thickness of Ti deposited for silicidation is set to about 30 nm, the final thickness of the silicide layer becomes 60 nm, the sheet resistance of the source / drain diffusion layer maintains 3Ω / □, and 0. This is almost the same as that in the 5 μm CMOS process.

When the gate width is 2.6 μm, the channel resistance of the transistor is about 1 kΩ, while the resistance of the source / drain diffusion layer is about 98 Ω. FIG.
In the layout of (b), the drain current is reduced by about 10%.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a MOS semiconductor device in which a drain current does not decrease when a salicide process is used in a deep submicron region or less and a MOS semiconductor device thereof. It is to provide a manufacturing method.

[0015]

A MOS semiconductor device of the present invention, a first conductivity type silicon layer having a main surface, and a gate insulating film selectively formed on the main surface of the silicon layer,
A MOS semiconductor device including a gate electrode provided on the gate insulating film, an insulating sidewall formed on a side portion of the gate electrode, and source / drain regions formed in the silicon layer. And the source / drain region is a first conductivity type first layer formed in the silicon layer.
A diffusion layer and a second conductivity type second diffusion layer formed outside the first diffusion layer in the silicon layer and having a junction depth deeper than the junction depth of the first diffusion layer. In addition, a conductive layer covering at least a part of the first diffusion layer and at least a part of the second diffusion layer is provided, thereby achieving the above object.

In one embodiment, the conductive layer has a first portion having a first thickness and a second portion having a second thickness greater than the first thickness, The first portion of the conductive layer covers the at least a portion of the second diffusion layer.

In one embodiment, the conductive layer is made of silicide.

In one embodiment, the gate electrode has a multilayer structure including a lower silicon film and an upper silicide film.

In one embodiment, the silicon layer is a single crystal semiconductor.

In one embodiment, the silicon layer is formed on a substrate having an insulating surface.

A method of manufacturing a MOS semiconductor device according to the present invention comprises a step of forming a gate insulating film on a silicon layer, a step of forming a gate electrode on the gate insulating film, and a second conductive film in the silicon layer. Forming a first diffusion layer of the mold,
Forming a spacer on a side portion of the gate electrode, and forming a spacer on the outer side of the first diffusion layer in the silicon layer, the second conduction type second layer having a junction depth deeper than a junction depth of the first diffusion layer. A step of forming a second diffusion layer, and further, before the step of forming the spacer, depositing a first conductor layer to be a first silicide layer covering at least a part of the first diffusion layer. And a step of depositing a second conductor layer to be a second silicide layer covering at least a part of the second diffusion layer after the step of forming the spacer, whereby the above object is achieved. To be achieved.

In one embodiment, the second conductor layer is deposited thicker than the first conductor layer.

In one embodiment, at least one of the first conductor layer and the second conductor layer is formed of a refractory metal, and the refractory metal is reacted with a part of the silicon layer, The first and second silicide layers are formed.

In one embodiment, at least one of the first conductor layer and the second conductor layer is formed of a refractory metal silicide layer.

A method of manufacturing a MOS semiconductor device according to the present invention comprises a step of forming an element isolation region on one main surface of a first conductivity type semiconductor substrate, a step of forming a gate insulating film on the semiconductor substrate, Depositing a first conductive film on the gate insulating film, patterning a photoresist at a predetermined position on the first conductive film to be a gate electrode, and using the photoresist as a mask A step of selectively etching a multilayer film including the gate insulating film and the first conductive film in the vertical direction by strong anisotropic etching until the gate insulating film is exposed; and a step of removing the photoresist. Depositing a first insulating film on the substrate and the gate electrode, and selectively leaving the first insulating film on the sidewall of the gate electrode by strong anisotropic anisotropic etching in the vertical direction; note Forming a diffusion layer of a first second conductivity type on the source / drain regions on the substrate by a method, and a second conductive film and a second insulating film on the substrate and the gate electrode. And the step of sequentially depositing the second conductive film in the vertical direction by strong anisotropic etching to form the second conductive film on the side wall of the gate electrode in an L shape and on the outer side of the second conductive film. The step of leaving the second insulating film and the second implantation having a junction deeper than the junction depth of the diffusion layer of the first second conductivity type in the source / drain region on the substrate by the ion implantation method. A step of forming a diffusion layer of two-conductivity type, and a film of the same kind as the second conductive film and thicker than the second conductive film on the substrate and the gate electrode. Depositing a third conductive film and removing the gate electrode and the source / drain regions of the substrate by a silicon And a step of sequentially removing the non-silicided third conductive film, the second insulating film, and the non-silicided second conductive film, Thereby, the above object is achieved.

A method of manufacturing a MOS semiconductor device according to the present invention comprises a step of forming an element isolation region on one main surface of a first conductivity type semiconductor substrate, a step of forming a gate insulating film on the semiconductor substrate, A step of depositing a first conductive film on the gate insulating film, a step of forming a photoresist on a predetermined position to be a gate electrode on the first conductive film, and using the photoresist as a mask, A step of selectively etching a multilayer film including the gate insulating film and the first conductive film until the gate insulating film is exposed by etching having a strong anisotropy in the vertical direction; Removing step, depositing a first insulating film on the substrate and the gate electrode, and selectively leaving the first insulating film on the sidewall of the gate electrode by strong anisotropic etching in the vertical direction. And the process Forming a second diffusion type first diffusion layer in the source / drain regions on the substrate by an ion implantation method, depositing a conductive film on the substrate and the gate electrode, and the gate electrode And a step of siliciding the source / drain regions of the substrate, a step of depositing a second insulating film on the substrate and the gate electrode, and selective anisotropic strong anisotropic etching, and the silicide. A step of leaving the second insulating film on the side wall of the gate electrode by dry etching having a sufficient selection ratio for the layer film, and a step of joining the first diffusion layer to the source / drain regions on the substrate by an ion implantation method. And a step of forming a second diffusion layer of the second conductivity type having a junction deeper than the depth, whereby the above object is achieved.

A method of manufacturing a MOS semiconductor device according to the present invention comprises a step of forming an element isolation region on one main surface of a first conductivity type semiconductor substrate, a step of forming a gate insulating film on the semiconductor substrate, A step of depositing a first conductive film on the gate insulating film, a step of forming a photoresist on a predetermined position to be a gate electrode on the first conductive film, and using the photoresist as a mask, A step of selectively etching the multilayer film including the gate insulating film and the first conductive film by strong anisotropic etching in the vertical direction until the gate insulating film is exposed; and removing the photoresist. Steps, steps of depositing a first insulating film on the substrate and the gate electrode, and steps of selectively leaving the first insulating film on the sidewalls of the gate electrode by strong anisotropic etching in the vertical direction. And ion injection Selectively forming a second conductive type first diffusion layer in the source / drain region on the substrate by a method, and depositing a second insulating film on the substrate and the gate electrode. A step of leaving the second insulating film on the side wall of the gate electrode by a strong anisotropic etching in the vertical direction; and a step of forming a junction depth of the first diffusion layer in a source / drain region on the substrate by an ion implantation method. Also, a step of forming a second diffusion layer of a second conductivity type having a deep junction, a step of depositing a first conductive film on the substrate and the gate electrode, a source of the gate electrode and the substrate The step of siliciding the / drain region, the step of removing the second insulating film, and the step of selectively growing the second conductive film on the non-silicided substrate, By doing so, the above object is achieved.

A method of manufacturing a MOS semiconductor device according to the present invention comprises a step of forming an element isolation region on one main surface of a first conductivity type semiconductor substrate, a step of forming a gate insulating film on the semiconductor substrate, A step of depositing a first conductive film on the gate insulating film, a step of forming a photoresist on a predetermined position to be a gate electrode on the first conductive film, and using the photoresist as a mask, A step of selectively etching the multilayer film including the gate insulating film and the first conductive film by strong anisotropic etching in the vertical direction until the gate insulating film is exposed; and removing the photoresist. Steps, steps of depositing a first insulating film on the substrate and the gate electrode, and steps of selectively leaving the first insulating film on the sidewalls of the gate electrode by strong anisotropic etching in the vertical direction. And ion injection Forming a second diffusion type first diffusion layer in the source / drain regions on the substrate by a method, and selectively depositing a first conductive film on the substrate and the gate electrode. Second on the substrate and the gate electrode
The step of depositing an insulating film, selective anisotropic strong etching in the vertical direction, and dry etching having a sufficient selective ratio to the first conductive film to form the second insulating film on the side wall of the gate electrode. And a step of forming a second diffusion layer of the second conductivity type having a junction deeper than the junction depth of the first diffusion layer in the source / drain regions on the substrate by ion implantation. Selectively depositing a second conductive film on the substrate and the first conductive film on the gate electrode, whereby the above object is achieved.

[0029]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a MOS type semiconductor device and a method of manufacturing the same according to the present invention will be described below with reference to the drawings.

(Embodiment 1 of MOS type semiconductor device) FIG.
FIG. 3 shows a cross section of a first embodiment of a MOS semiconductor device according to the present invention.

The MOS semiconductor device of FIG. 1 includes a P-type semiconductor substrate 1, a gate insulating film 3 formed on the P-type semiconductor substrate 1, a gate electrode 4 provided on the gate insulating film 3, and a gate electrode 4. SiO ₂ sidewall 5 formed on the side
a and 5b, an N-type source / drain diffusion layer 6 having a shallow junction provided in the source / drain region of the P-type semiconductor substrate 1, and a deep junction provided in the source / drain region of the P-type semiconductor substrate 1. The N-type source / drain diffusion layer 7 and the gate electrode 4 and the silicide layers 8a and 8b formed in the source / drain regions are provided.

Although only a single N-channel MOS type semiconductor device is shown in FIG. 1, a plurality of MOS type semiconductor devices are actually formed on one P-type semiconductor substrate 1. Each of these MOS type semiconductor devices has a structure shown in the drawing and is electrically isolated from each other by a trench isolation structure 2 formed in a P type semiconductor substrate 1.
An N-type well may be provided in the P-type semiconductor substrate 1 and a P-channel MOS type semiconductor device may be formed in the N-type well.
Note that instead of the silicon substrate, a MOS type semiconductor device (thin film transistor) may be formed by using a silicon layer formed on a substrate (glass substrate or the like) having an insulating surface.

The first characteristic of the MOS type semiconductor device of FIG. 1 is that the silicide layer 8a is provided so as to cover at least a part of the shallow source / drain diffusion layer 6. Although the conventional silicide layer is formed on the deep source / drain diffusion layer 7, it is not formed on the shallow source / drain diffusion layer 6. In this embodiment, since the silicide layer (8a) covers at least a part of the upper surface of the shallow source / drain diffusion layer 6, preferably about half the area, the source / drain resistance is reduced as a whole. As a result, even if the number of source / drain contacts assigned to each transistor is set to one, the drain current hardly decreases.

The second feature is that the silicide layer is composed of portions having two different thicknesses. A relatively thin silicide layer 8a is provided on the source / drain diffusion layer 6 having a shallow junction, and a relatively thick silicide layer 8b is provided on the source / drain diffusion layer 7 having a deep junction. . Therefore, the formation of the silicide layer does not adversely affect the PN junction formed between the source / drain diffusion layers 6 and 7 and the semiconductor substrate 1. if,
If a silicide layer having the same thickness as the relatively thick silicide layer 8b is provided on the source / drain diffusion layer 6 having a shallow junction, it is considered that the leak current generated through the PN junction may increase. . In order to avoid an increase in leak current, the thickness (final thickness) of the silicide layer 8a provided on the source / drain diffusion layer 6 having a shallow junction should be set to the junction depth of the source / drain diffusion layer 6. About 20
It is preferably set to about 50%.

In order to investigate the effect of the present invention, consider a CMOS process having a design rule of 0.13 μm. For example, the gate length is 0.13 μm and the gate oxide film thickness is 4 nm. The junction depth of the shallow source / drain diffusion layer is set to about 80 nm and the impurity concentration on the surface is set to 1.0 × 10 ²⁰ cm ⁻³ in order to suppress the short channel effect and the high drain current. The width of the sidewall is about 30 nm. On the other hand, the junction depth of the deep source / drain diffusion layer is set to about 120 nm, and the impurity concentration on the surface is set to 2.0 × 10 ²⁰ cm ⁻³ . The thickness of Ti deposited for silicidation is 30 n in the thick portion.
m and 20 nm in the thin portion. The reason why the thickness is set to 20 nm in the thin portion is to suppress the leakage current and suppress a large increase in the source / drain resistance. The thickness of the final silicide layer is 60 nm in the thick part and 40 in the thin part.
nm. The thick portion of the silicide layer is 80 nm thick,
The thin part becomes 90 nm.

Based on the above design, the sheet resistance of the source / drain diffusion layer is calculated to be 3Ω / □ in the thick part and 4Ω / □ in the thin part. When the gate width is 2.6 μm, the channel resistance of the transistor is about 1 kΩ.

According to the conventional example, the resistance of the source / drain region is about 98Ω, and when the layout of FIG. 8B is adopted, the drain current is reduced by about 10%. On the other hand, according to the present invention, the resistance of the source / drain region is reduced to about 53Ω, so that the drain current is reduced by about 5%.

Although Ti is used as the conductive material for forming the silicide layer in the present invention, other refractory metals such as Co and Ni may be used. Further, instead of the silicide layer, a layer made of a refractory metal such as W may be used. In addition, W formed by selectively forming only the thin portion of the silicide layer
You may replace with the layer which consists of refractory metals, such as.

The above embodiment is based on the N-channel type MOS.
Although it is a transistor, the conductivity type may be the same as that used in the above embodiment.

(Second Embodiment of MOS Semiconductor Device) FIG.
FIG. 8 shows a sectional view of a second embodiment of a MOS type semiconductor device according to the present invention.

The MOS type semiconductor device of FIG. 2 includes a P type semiconductor substrate 1, a gate insulating film 3 formed on the P type semiconductor substrate 1, a gate electrode 4 provided on the gate insulating film 3 and a gate electrode 4. SiO ₂ sidewall 5 formed on the side
a and 5b, an N-type source / drain diffusion layer 6 having a shallow junction provided in the source / drain region of the P-type semiconductor substrate 1, and a deep junction provided in the source / drain region of the P-type semiconductor substrate 1. It has an N-type source / drain diffusion layer 7, and a gate electrode 4 and a silicide layer 8 formed in the source / drain regions.

Although only a single MOS type semiconductor device is shown in FIG. 2, one P type semiconductor substrate 1 is actually used.
A plurality of MOS semiconductor devices are formed in the. Each of these MOS type semiconductor devices has a structure shown in the drawing and is electrically isolated from each other by a trench isolation structure 2 formed in a P type semiconductor substrate 1.

The first characteristic of the MOS type semiconductor device of FIG. 2 is that the silicide layer 8 is provided so as to cover at least a part of the shallow source / drain diffusion layer 6.
The conventional silicide layer is a deep source / drain diffusion layer 7
However, it is not formed on the shallow source / drain diffusion layer 6.

In this embodiment, the silicide layer 8 having a low resistance is used.
Covers at least a part of the shallow source / drain diffusion layer 6, so that the source / drain resistance is reduced. As a result, even if the number of source / drain contacts assigned to each transistor is set to one, the drain current hardly decreases. In order to avoid a junction leak, it is preferable that the thickness of the silicide layer 8 be smaller than the thickness of the silicide layer 8b in the above-described embodiment.

In order to investigate the effect of the present invention, a CMOS process whose design rule is 0.13 μm is considered here. For example, the gate length is 0.13 μm and the gate oxide thickness is 4 nm. In order to suppress the short channel effect and the high drain current, the junction depth of the shallow source / drain diffusion layer is set to about 80 nm, and the impurity concentration on the surface is set to 1.0 × 10 ²⁰ cm ⁻³ . The width of the sidewall is about 30 nm. On the other hand, the junction depth of the deep source / drain diffusion layer is about 120 nm, and the impurity concentration on the surface is 2.0 × 10 ²⁰ cm ⁻³ . The thickness of Ti deposited for silicidation is 20 nm. The reason for making the thickness relatively thin is to suppress the leakage current. The final silicide layer thickness is 40n
It becomes m. The width of the silicide layer is 170 nm.

Based on the above design, the sheet resistance of the source / drain diffusion layer is calculated to be 4Ω / □. When the gate width is 2.6 μm, the channel resistance of the transistor is about 1 kΩ. According to the conventional example, the resistance of the source / drain region is about 98Ω, and when the layout of FIG. 8B is adopted, the drain current is reduced by about 10%. On the other hand, according to the present invention, the resistance of the source / drain region is reduced to about 53Ω, so that the drain current is reduced by about 6%.

In the present invention, Ti is used as the material of the silicide layer, but other refractory metals such as Co and Ni may be used. Further, instead of the silicide layer, a layer made of a refractory metal such as W may be used. Further, only the thin portion of the silicide layer may be replaced with a layer made of a refractory metal such as W selectively formed.

(First Embodiment of Manufacturing Method of MOS Type Semiconductor Device) Referring to FIGS. 3A to 3E, a first embodiment of a method of manufacturing the MOS type semiconductor device of FIG. explain.

First, as shown in FIG. 3A, a shallow trench isolation structure 2 having a depth of about 600 nm is formed in an element isolation region on a P-type semiconductor substrate 1. Next, the gate insulating film 3 is formed on the P-type semiconductor substrate 1 to have a thickness of about 4 nm, and the undoped polycrystalline silicon film 4 is deposited on the gate insulating film 3 to have a thickness of about 200 nm. Next, a photoresist mask that defines the shape and position of the gate electrode 4 is formed on the polycrystalline silicon film 4 by using the photolithography technique. After that, by etching having a strong anisotropy in the vertical direction (anisotropic etching), a portion of the polycrystalline silicon film 4 which is not covered with the photoresist mask is selectively removed to form a gate made of polycrystalline silicon. The electrode 4 is formed. Then, the photoresist mask is removed. After depositing an HTO film of about 30 nm so as to cover the gate electrode 4, the flat portion of the HTO film is selectively removed by anisotropic etching to form a relatively thin SiO ₂ sidewall 5a from the HTO film. Next, the dose amount is 4 × 10 ^14.
cm ⁻² N-type impurity ions (eg As ions)
Is implanted into the P-type semiconductor substrate 1 with an acceleration energy of 10 keV, thereby forming the N-type diffusion layer 6 having a shallow junction in the source / drain regions. The N-type diffusion layer 6 having a shallow junction may be formed before the SiO ₂ sidewall 5a is formed.

Next, as shown in FIG. 3B, the first T
The i / TiN film 9a has a thickness of about 20 nm, and the nitride film 10 has a thickness of 70 n.
About m are sequentially deposited. Here, the Ti / TiN film is a multilayer film having a Ti layer as a lower layer and a TiN layer as an upper layer.

Next, as shown in FIG. 3C, the nitride film 10 and the first Ti / TiN film are anisotropically etched.
The flat portion of the layer 9a is removed and the sidewall of the nitride film 10 is formed. At this time, Ti in the lower layer of the first Ti / TiN layer 9a does not need to be completely removed. First T
The portion of the i / TiN layer 9a covered with the sidewall of the nitride film 10 remains without being removed. After that, N-type impurity ions (for example, As ions) having a dose amount of about 6 × 10 ¹⁵ cm ⁻² are implanted into the P-type semiconductor substrate 1 at an acceleration energy of 60 keV, thereby forming deep junctions in the source / drain regions. The N-type diffusion layer 7 having is formed. At the time of this ion implantation, the N-type impurity ions are simultaneously implanted into the gate electrode 4 to give the gate electrode 4 high conductivity.

Next, as shown in FIG. 3D, the second T
The i / TiN layer 9b is deposited to about 30 nm. After this,
First RTA (Rapid Thermal Anneal) at 700 ℃, 3
Performed under the condition of 0 sec, followed by the second RTA
Is performed at 1000 ° C. for 10 seconds. As a result of this two-step annealing, silicidation is performed at the same time as the activation of the impurities implanted in the source / drain regions and the gate electrode 4. This silicidation is caused by the first Ti / TiN layer 9a.
And in the portion of the second Ti / TiN layer 9b that is in contact with silicon. First, the second Ti / TiN layer 9
After the portion of b that has not been silicidized is removed with hydrofluoric acid, the sidewalls of the nitride film 10 are removed with hot phosphoric acid or isotropic dry etching. After that, the portion of the first Ti / TiN layer 9a that has not been silicidized is removed with hydrofluoric acid. Thus, as shown in FIG. 3E, a salicide structure including the silicides 8a and 8b is formed.

According to this embodiment, two kinds of silicide layers having different thicknesses can be formed in a self-aligned manner without additionally using a special mask.

In the present invention, Ti is used as the conductive material for forming the silicide layer, but a refractory metal such as Co or Ni may be used.

(Second Embodiment of Method for Manufacturing MOS Type Semiconductor Device) Referring to FIGS. 4A to 4D, a first embodiment of a method for manufacturing the MOS type semiconductor device of FIG. explain.

First, as shown in FIG. 4A, a shallow trench isolation structure 2 having a depth of about 600 nm is formed in an element isolation region on a P-type semiconductor substrate 1. Next, the gate insulating film 3 is formed on the P-type semiconductor substrate 1 to have a thickness of about 4 nm, and the undoped polycrystalline silicon film 4 is deposited on the gate insulating film 3 to have a thickness of about 200 nm. Next, a photoresist mask that defines the shape and position of the gate electrode 4 is formed on the polycrystalline silicon film 4 by using the photolithography technique. After that, by etching having a strong anisotropy in the vertical direction (anisotropic etching), a portion of the polycrystalline silicon film 4 which is not covered with the photoresist mask is selectively removed to form a gate made of polycrystalline silicon. The electrode 4 is formed. Then, the photoresist mask is removed. After depositing an HTO film of about 30 nm so as to cover the gate electrode 4, the flat portion of the HTO film is selectively removed by anisotropic etching to form a relatively thin SiO ₂ sidewall 5a from the HTO film. Next, the dose amount is 4 × 10 ^14.
cm ⁻² N-type impurity ions (eg As ions)
Is implanted into the P-type semiconductor substrate 1 with an acceleration energy of 10 keV, thereby forming the N-type diffusion layer 6 having a shallow junction in the source / drain regions.

Next, as shown in FIG. 4 (b), Ti / T
The iN film 9 is deposited to a thickness of about 20 nm.

Next, as shown in FIG. 4C, the first R
TA (Rapid Thermal Anneal) 700 ℃, 30sec
Under the conditions of. As a result of this anneal, silicidation is performed simultaneously with the activation of the impurities implanted in the source / drain regions and the gate electrode 4. This silicidation is
It occurs in the portion of the i / TiN layer 9 that is in contact with silicon. After removing the non-silicided portion of the Ti / TiN layer 9 with hydrofluoric acid, an HTO film of about 90 nm is deposited so as to cover the gate electrode 4, and then the flat portion of the HTO film is selectively etched by anisotropic etching. Removed to HT
A relatively thick SiO ₂ sidewall 5b is formed from the O film.

Next, N with a dose amount of about 6 × 10 ¹⁵ cm ^-2 is used.
-Type impurity ions (for example, As ions) are implanted into the P-type semiconductor substrate 1 at an acceleration energy of 60 keV, thereby forming an N-type diffusion layer 7 having a deep junction in the source / drain regions, and at the same time forming a gate electrode. An N-type polysilicon gate electrode 4 is formed by doping As ions.
Finally, perform the second RTA at 1000 ° C for 10 seconds,
The activation of the impurities implanted in the source / drain regions and the gate electrode 4 is completed.

According to this embodiment, it is possible to form two kinds of silicide layers having different thicknesses in a self-aligned manner without additionally using a special mask. Also, the first T
Since the thickness of the i / TiN layer 9a and the thickness of the second Ti / TiN layer 9b can be set independently of each other, the degree of freedom in design is increased.

Although Ti is used as the conductive material for forming the silicide layer in the present invention, a refractory metal such as Co or Ni may be used.

(Third Embodiment of Manufacturing Method of MOS Type Semiconductor Device) With reference to FIGS. 5A to 5D, an embodiment of a method of manufacturing a device similar to the MOS type semiconductor device of FIG. Will be explained.

First, as shown in FIG. 5A, a shallow trench isolation structure 2 having a depth of about 600 nm is formed in an element isolation region on a P-type semiconductor substrate 1. Next, the gate insulating film 3 is formed on the P-type semiconductor substrate 1 to have a thickness of about 4 nm, and the undoped polycrystalline silicon film 4 is deposited on the gate insulating film 3 to have a thickness of about 200 nm. Next, a photoresist mask that defines the shape and position of the gate electrode 4 is formed on the polycrystalline silicon film 4 by using the photolithography technique. After that, by etching having a strong anisotropy in the vertical direction (anisotropic etching), a portion of the polycrystalline silicon film 4 which is not covered with the photoresist mask is selectively removed to form a gate made of polycrystalline silicon. The electrode 4 is formed. Then, the photoresist mask is removed. After depositing an HTO film of about 30 nm so as to cover the gate electrode 4, the flat portion of the HTO film is selectively removed by anisotropic etching to form a relatively thin SiO ₂ sidewall 5a from the HTO film. Next, the dose amount is 4 × 10 ^14.
cm ⁻² N-type impurity ions (eg As ions)
Is implanted into the P-type semiconductor substrate 1 with an acceleration energy of 10 keV, thereby forming the N-type diffusion layer 6 having a shallow junction in the source / drain regions.

Next, a nitride film is deposited to a thickness of about 90 nm so as to cover the gate electrode 4, and the flat portion of the nitride film is selectively removed by anisotropic etching to obtain a relatively thick nitride film 1.
A 0 sidewall is formed. After this, the dose amount 6 ×
N-type impurity ions (for example, As ions) of about 10 ¹⁵ cm ⁻² are implanted into the P-type semiconductor substrate 1 at an acceleration energy of 60 keV, whereby the N-type diffusion layer 7 having a deep junction in the source / drain regions. At the same time, the gate electrode is doped with As ions to form an N-type polysilicon gate electrode 4.

First RTA (Rapid Thermal Anneal) is performed at 1000 ° C. for 10 seconds. As a result of this anneal, silicidation is performed simultaneously with the activation of the impurities implanted in the source / drain regions and the gate electrode 4.
This silicidation occurs in the portion of the Ti / TiN layer 9 that is in contact with silicon.

Next, after depositing a Ti / TiN layer 9 to a thickness of about 20 nm, a second RTA is performed at 700 ° C. to silicify the gate and the source / drain. The silicide layer 8 is formed by etching the unsilicided Ti / TiN layer 9 with hydrofluoric acid.

After that, the sidewalls of the nitride film 10 are etched by hot phosphoric acid or isotropic dry etching, and then the portions not covered with the silicide, that is, the P-type substrate having the sidewalls of the nitride film 10 are etched. 1, a W layer is selectively grown to a thickness of about 20 nm. W layer is WF ₆ /
It is formed by a CVD method using SiH ₄ gas.

The device manufactured in this way is
The same effect as the embodiment of FIG. 1 is exhibited. Further, according to the present embodiment, since the silicidation is performed after the activation of the impurities implanted in the source / drain regions and the gate electrode, the silicidation process conditions can be selected from a wide range.

(Fourth Embodiment of Method of Manufacturing MOS-Type Semiconductor Device) Another method of manufacturing a device similar to the MOS-type semiconductor device of FIG. 1 will be described with reference to FIGS. 6A to 6D. An example will be described.

First, as shown in FIG. 6A, a shallow trench isolation structure 2 having a depth of about 600 nm is formed in an element isolation region on a P-type semiconductor substrate 1. Next, the gate insulating film 3 is formed on the P-type semiconductor substrate 1 to have a thickness of about 4 nm, and the undoped polycrystalline silicon film 4 is deposited on the gate insulating film 3 to have a thickness of about 200 nm. Next, a photoresist mask that defines the shape and position of the gate electrode 4 is formed on the polycrystalline silicon film 4 by using the photolithography technique. After that, by etching having a strong anisotropy in the vertical direction (anisotropic etching), a portion of the polycrystalline silicon film 4 which is not covered with the photoresist mask is selectively removed to form a gate made of polycrystalline silicon. The electrode 4 is formed. Then, the photoresist mask is removed. After depositing an HTO film of about 30 nm so as to cover the gate electrode 4, the flat portion of the HTO film is selectively removed by anisotropic etching to form a relatively thin SiO ₂ sidewall 5a from the HTO film. Next, the dose amount is 4 × 10 ^14.
cm ⁻² N-type impurity ions (eg As ions)
Is implanted into the P-type semiconductor substrate 1 with an acceleration energy of 10 keV, thereby forming the N-type diffusion layer 6 having a shallow junction in the source / drain regions.

Next, as shown in FIG.
The first selective W layer 11a is selectively grown to a thickness of about 20 nm on the drain region and the gate electrode 4. At this time, W is formed by the CVD method using WF ₆ / SiH ₄ gas.

Next, as shown in FIG. 6C, after depositing an HTO film of about 90 nm, a thick SiO ₂ sidewall 5b is formed by anisotropic etching. After that, N type impurity ions (for example, As ions) having a dose amount of about 6 × 10 ¹⁵ cm ⁻² are accelerated with an acceleration energy of 60 keV.
To p-type semiconductor substrate 1.
The N-type diffusion layer 7 having a deep junction is formed in the drain region, and at the same time, the gate electrode is doped with As ions to form the N-type polysilicon gate electrode 4.

Further, RTA is performed at 1000 ° C. for 10 seconds to simultaneously activate the impurities implanted in the source / drain regions and the gate electrode 4.

Next, as shown in FIG.
The second selection W layer 11b is selectively formed on the first selection W layer exposed on the drain region and the gate electrode.
Is grown to about 20 nm.

The shallow source / drain diffusion layer of the device thus manufactured has a diffusion thickness of 80 nm and the impurity concentration on the surface is 1.0 × 10 ²⁰ cm ^-3 . Deep sauce /
The junction depth of the drain diffusion layer is 120 nm, and the impurity concentration on the surface is 2.0 × 10 ²⁰ cm ⁻³ . The thick part of the W layer is 40 nm, the thin part is 20 nm, and the thin part is W
Has a width of 90 nm.

The sheet resistance of the source / drain diffusion layer is 2 Ω / □ in the thick portion and 4 Ω / □ in the thin portion. Thin O
Assuming that the width of D is 0.2 μm, the width of W in the thick portion is 80 nm. If the gate length is 0.13 μm and the gate width is 2.6 μm, the channel resistance of the transistor is about 1 kΩ. The resistance of OD in the conventional example is about 98.
In the layout of FIG. 8B, the drain current deteriorates by about 10%, while the OD of the present invention is Ω.
Resistance can be reduced to about 42Ω, and the deterioration of the drain current is about 4%.

This embodiment has an advantage that the thickness of the selective W layer can be freely set without depending on the junction depth of the source / drain diffusion layers because the silicide layer is not used.
As a result, the thickness of the first selection W layer can be suppressed to such an extent that the capacitance between the gate and the drain does not increase so much, and the thickness of the second selection W layer can be increased to such an extent that the source / drain resistance can be sufficiently reduced.

In the deep sub-micron region and below, a semiconductor device using the current LSI technology is used, in which the source / drain contact is reduced to one and the drain current is not deteriorated when the width of the source / drain is reduced. Thus, it can be easily manufactured in a self-aligning manner.

[0079]

According to the semiconductor device of the present invention, the source / drain resistance can be reduced because the shallow source / drain diffusion layer and the deep source / drain diffusion layer have a silicide layer or a metal which has not existed in the prior art. It is possible to prevent a decrease in drain current that occurs when the number of source / drain contacts is one.

According to the method of manufacturing a semiconductor device of the present invention,
In the deep sub-micron region and below, a semiconductor device that does not cause the deterioration of the drain current caused by narrowing the width of the source / drain with one source / drain contact is self-aligned using the current LSI technology. Can be easily manufactured.

[Brief description of drawings]

FIG. 1 is a structural sectional view showing an embodiment of a MOS type semiconductor device of the present invention.

FIG. 2 is a structural cross-sectional view showing another embodiment of the MOS semiconductor device of the present invention.

3 (a) to 3 (e) are structural sectional views showing an embodiment of a method for manufacturing a MOS semiconductor device of the present invention.

4A to 4D are structural cross-sectional views showing another embodiment of the method for manufacturing a MOS type semiconductor device of the present invention.

5A to 5D are structural cross-sectional views showing still another embodiment of the method for manufacturing a MOS semiconductor device of the present invention.

6 (a) to 6 (d) are structural cross-sectional views showing still another embodiment of the method for manufacturing a MOS type semiconductor device of the present invention.

FIG. 7 is a structural cross-sectional view showing a conventional MOS type semiconductor device.

FIG. 8 is a plan layout view of a conventional MOS semiconductor device with and without a salicide process.

[Explanation of symbols]

1 P-type semiconductor substrate 2 Trench isolation 3 Gate insulating film 4 Gate electrode 5 SiO ₂ sidewall 5a Thin SiO ₂ sidewall 5b Thick SiO ₂ sidewall 6 Shallow N-type high-concentration diffusion layer 7 Deep N-type high-concentration diffusion layer 8 Silicide 8a thin silicide 8b thick silicide 9 Ti / TiN layer 9a first Ti / TiN layer 9b second Ti / TiN layer 10 Si ₃ N ₄ film 11 selective W layer 11a thin selective W layer 11b thick selective W layer

Claims (14)

[Claims] 1. A first conductivity type silicon layer having a main surface, a gate insulating film selectively formed on the main surface of the silicon layer, a gate electrode provided on the gate insulating film, Insulating sidewalls formed on the sides of the gate electrode, source / drain regions formed in the silicon layer,
A source / drain region is formed in the silicon layer outside the first diffusion layer, and a second conductivity type first diffusion layer formed in the silicon layer; Is
A second diffusion layer of a second conductivity type having a junction depth deeper than the junction depth of the first diffusion layer, and at least a part of the first diffusion layer and the second diffusion layer. A MOS semiconductor device comprising a conductive layer covering at least a part of the. 2. The first conductive layer has a first thickness.
A second portion having a second thickness greater than the first thickness, the first portion of the conductive layer covering the at least a portion of the second diffusion layer. The MOS semiconductor device according to claim 1, wherein 3. The MOS semiconductor device according to claim 1, wherein the conductive layer is made of silicide. 4. The gate electrode has a multilayer structure including a lower silicon film and an upper silicide film.
The MOS-type semiconductor device according to 1. 5. The MOS semiconductor device according to claim 1, wherein the silicon layer is a single crystal semiconductor. 6. The MOS semiconductor device according to claim 1, wherein the silicon layer is formed on a substrate having an insulating surface. 7. A step of forming a gate insulating film on a silicon layer, a step of forming a gate electrode on the gate insulating film, and a step of forming a second diffusion type first diffusion layer in the silicon layer. And a step of forming a spacer on a side portion of the gate electrode, and a step of forming a spacer on the outer side of the first diffusion layer in the silicon layer.
Forming a second diffusion layer of a second conductivity type having a junction depth deeper than the junction depth of the diffusion layer, and further comprising the step of forming the spacer before the step of forming the spacer. A step of depositing a first conductor layer to be a first silicide layer covering at least a part of the layer, and a step of forming the spacer to be a second silicide layer covering at least a part of the second diffusion layer. And a step of depositing a second conductor layer. 8. The method for manufacturing a MOS semiconductor device according to claim 7, wherein the second conductor layer is deposited thicker than the first conductor layer. 9. At least one of the first conductor layer and the second conductor layer is formed of a refractory metal, and the refractory metal is allowed to react with a part of the silicon layer to form the first conductor layer. 9. The method for manufacturing a MOS semiconductor device according to claim 7, wherein the second silicide layer is formed. 10. The method for manufacturing a MOS semiconductor device according to claim 7, wherein at least one of the first conductor layer and the second conductor layer is formed of a refractory metal silicide layer. 11. A step of forming an element isolation region on one main surface of a first conductivity type semiconductor substrate, a step of forming a gate insulating film on the semiconductor substrate, and a first conductivity type on the gate insulating film. A step of depositing a film, a step of patterning a photoresist at a predetermined position to be a gate electrode on the first conductive film, a step of using the photoresist as a mask, the gate insulating film and the first conductive film A step of selectively etching a multi-layered film made of a film in the vertical direction by strong anisotropic etching until the gate insulating film is exposed; a step of removing the photoresist; a first step on the substrate and the gate electrode. By the step of depositing the insulating film of FIG.
Leaving the insulating film on the side wall of the gate electrode, forming a first second conductivity type diffusion layer in the source / drain regions on the substrate by an ion implantation method, and the substrate and the substrate. A second conductive film on the gate electrode, and a second conductive film
Second insulating film is sequentially deposited, and the second anisotropic etching is selectively performed in the vertical direction.
A conductive film of L-shape on the side wall of the gate electrode, and leaving the second insulating film outside the second conductive film; A step of forming a second diffusion layer of the second conductivity type having a junction deeper than the junction depth of the diffusion layer of the first second conductivity type in the drain region; Depositing a third conductive film of the same type as the second conductive film and having a thickness larger than that of the second conductive film, and the gate electrode and the source / source of the substrate. A step of siliciding the drain region, and a step of sequentially removing the non-silicided third conductive film, the second insulating film, and the non-silicided second conductive film. And a method for manufacturing a MOS semiconductor device including the following. 12. A step of forming an element isolation region on one main surface of a first conductivity type semiconductor substrate, a step of forming a gate insulating film on the semiconductor substrate, and a first conductivity type on the gate insulating film. A step of depositing a film, a step of forming a photoresist at a predetermined position to be a gate electrode on the first conductive film, a step of using the photoresist as a mask, the gate insulating film and the first conductive film A multi-layered film made of a film is selectively etched until the gate insulating film is exposed by etching having a strong anisotropy in the vertical direction, a step of removing the photoresist, the substrate and the gate. The step of depositing a first insulating film on the electrode and the anisotropic anisotropic etching selectively in the vertical direction
Leaving the insulating film on the side wall of the gate electrode, forming a second diffusion type first diffusion layer in the source / drain regions on the substrate by ion implantation, the substrate and the gate Depositing a conductive film on the electrode, siliciding the gate electrode and the source / drain regions of the substrate, depositing a second insulating film on the substrate and the gate electrode, A step of leaving the second insulating film on the side wall of the gate electrode by selective anisotropic anisotropic etching and dry etching having a sufficient selection ratio to the silicide layer film; Forming a second diffusion layer of the second conductivity type having a junction deeper than the junction depth of the first diffusion layer in the source / drain region on the substrate.
A method for manufacturing an OS type semiconductor device. 13. A step of forming an element isolation region on one main surface of a first conductivity type semiconductor substrate, a step of forming a gate insulating film on the semiconductor substrate, and a first conductivity type on the gate insulating film. A step of depositing a film, a step of forming a photoresist at a predetermined position to be a gate electrode on the first conductive film, a step of using the photoresist as a mask, the gate insulating film and the first conductive film A step of selectively etching the multi-layered film of films by strong anisotropic etching in the vertical direction until the gate insulating film is exposed; a step of removing the photoresist; and a step of removing the photoresist on the substrate and the gate electrode. A step of depositing a first insulating film on the first and a strong anisotropic etching in the vertical direction selectively,
Leaving the insulating film on the side wall of the gate electrode, forming a second diffusion type first diffusion layer in the source / drain regions on the substrate by ion implantation, the substrate and the gate A step of depositing a second insulating film on the electrode and a step of selectively anisotropically etching in the vertical direction
A step of leaving the insulating film on the side wall of the gate electrode, and a second conductivity type second junction having a junction deeper than the junction depth of the first diffusion layer in the source / drain region on the substrate by an ion implantation method. 2 a step of forming a diffusion layer, a step of depositing a first conductive film on the substrate and the gate electrode, a step of siliciding the gate electrode and the source / drain region of the substrate, 2. A method for manufacturing a MOS semiconductor device, comprising: a step of removing the second insulating film; and a step of selectively growing a second conductive film on the non-silicided substrate. 14. A step of forming an element isolation region on one main surface of a first conductivity type semiconductor substrate, a step of forming a gate insulating film on the semiconductor substrate, and a first conductivity type on the gate insulating film. A step of depositing a film, a step of forming a photoresist at a predetermined position to be a gate electrode on the first conductive film, a step of using the photoresist as a mask, the gate insulating film and the first conductive film A step of selectively etching the multi-layered film of films by strong anisotropic etching in the vertical direction until the gate insulating film is exposed; a step of removing the photoresist; and a step of removing the photoresist on the substrate and the gate electrode. A step of depositing a first insulating film on the first and a strong anisotropic etching in the vertical direction selectively,
Leaving the insulating film on the side wall of the gate electrode, forming a second diffusion type first diffusion layer in the source / drain regions on the substrate by ion implantation, the substrate and the gate Selectively depositing a first conductive film on the electrodes, depositing a second insulating film on the substrate and the gate electrode, and selectively anisotropically strong anisotropic etching; A step of leaving the second insulating film on the side wall of the gate electrode by dry etching with a sufficient selection ratio for the first conductive film; and a step of forming the second insulating film on the source / drain region on the substrate by ion implantation. Forming a second conductivity type second diffusion layer having a junction deeper than the junction depth of the first diffusion layer, and selectively forming a second diffusion layer on the substrate and the first conductive film on the gate electrode. 2 depositing a conductive film
A method for manufacturing an OS type semiconductor device.