JPH01295331A - Multiplier - Google Patents

Abstract

PURPOSE:To obtain a high-speed multiplier despite the simplification of hard ware by forming a multiplication circuit with combination of logical elements and performing the multiplication with use of a fixed multiplier. CONSTITUTION:Each of unit circuits 1-5 output the product Y together with two bits B00 and B01 as the residual to the input of three bits (BI, A and B) as the result of multiplication of a 1/3 fixed multiplier. When all inputs are equal to '0', all outputs are also equal to '0'. When the least significant bit 'B' of the input is equal to '1', the product Y is equal to '0' together with the bits B01 and B00 equal to '0' and '1' respectively. In case only A of the input is equal to '1', the product Y is equal to '0' with the bits B01 and B00 equal to '1' and '0' respectively. In such a way, a multiplication circuit formed with combination of logical elements can calculate the results of multiplication with the multiplicand inputs X1-X4 with no input of multiplication, i.e., a fixed number. Then it is not required to produce the partial products and to add these products together.

Description

Detailed Description of the Invention (Industrial Application W) This invention provides a multiplier that multiplies input data of multiple bits, especially when the multiplier is a constant. It concerns a multiplier that can obtain .

[Prior art] Figure 4 shows the circuit system of a multiplier based on the parallel operation method, which is increasingly becoming rLsI,'' Nikkei Electronics, 1.
This figure shows a conventional 4×4 bit multiplier as shown on May 29, 1978, pages 76 to 90. In the figure, (21) is a unit circuit that generates partial products and adds partial products; (22
), (23), and (24) are unit circuits that perform corrections resulting from multiplication using this complement representation, (X, ), (x-)
, (x-), (x4) are the multiplicand inputs during multiplication,
Of these, (x4) is the sign bit of this complement, (yt)
, (y2), (y3), (y4) are the multiplier inputs for multiplication, among which (y4) is the sign bit of this complement, (
Ps), (P2), (P, ), (P4), (Ps)-(
Pa) and (P,) are the multiplication result outputs. Note that the [phase] marks attached to the unit circuits (22) and (23) in the figure are invert inputs.

FIG. 5 is a block diagram of a unit circuit constituting the multiplier of FIG. 4, in which (25) is an AND gate, (26)
is a full adder, (k) is the input of the previous stage addition result, (X) is the multiplicand, (y) is the multiplier, (C) is the carry manual, (Co) is the carry output, and (P) is the partial product addition result output. be.

A conventional multiplier is constructed as described above, with a multiplicand input (X
When t) to (X4) and multiplier inputs (yt) to (y4) are input, the unit circuit (21) generates and adds partial products of the numerical part, and the unit circuits (22) and (23)
), (24) perform the correction resulting from the multiplication by this complement representation, and the sum of the partial products of the numerical part and the calculation result of the correction part is the multiplication result output (p+) ~ (P7
) is output as

(Problem to be solved by the invention) Since the conventional multiplier is configured as described above,
Correction for this complement representation is necessary and addition of partial products must be performed, so there are problems such as the need to provide hardware for this and the time required for it.

This invention was made to solve these problems, and it is possible to perform this complement representation without correction, eliminate the need to generate or add partial products, and obtain multiplication results at high speed. The purpose is to obtain a multiplier whose configuration can be simplified.

(Means for Solving the Problems) A multiplier according to the present invention is a multiplier that outputs the result of multiplying a multiplicand input of multiple bits by a multiplier. A multiplication circuit is provided to calculate the result of multiplication with .

(Function) In the present invention, the multiplication result of the multiplicand is calculated by the multiplication circuit configured by a combination of logic elements without inputting a fixed number of multiplications, and the partial products are generated and added. does not require

(Embodiment) Fig. 1 shows a multiplier according to an embodiment of the present invention, which is a multiplier that multiplies a 4-bit multiplicand.
In the figure, the same reference numerals as in Fig. 4 indicate the same or corresponding parts.
1) is the unit circuit for this complement representation, (2), (3)
, (4), and (5) are unit circuits that perform calculations on the numerical part,
are cascaded together.

Figure 2 shows each unit circuit (1) constituting the multiplier in Figure 1.
~(5) is a logic circuit diagram, in which (A), CB) are multiplicable inputs, (Bl) is the borrow power, and (Y) is the product obtained by multiplying the above 3-bit input by the multiplication of the station. , (BOG), (
BOI) is borrow output, (6), (7), (8) are N
AND gate, (9) is NOT gate, (1o) is OR
gate, (11) is NOR gate, (12) is Ex-O
R (Exclusive OR) gate, (13) is A
It is an ND gate.

In the multiplier configured as described above, the unit circuit operates as follows. That is, each unit circuit (1) ~
(5) is the product of the 3-bit inputs (81), (A), and (B) multiplied by the station's fixed multiplier (Y), and the remainder (no.) and 2-bit (BOl). is outputting.

When the inputs are all 0, the outputs are also all 0. When the least significant bit rBj of the input is 1, the product Y is 01
Of the remaining 2 bits, (Bob) is 1 (80°)
bawl.

When only (A) among the inputs is 1, the product (Y) is O
Of the 2 bits with a remainder of 1, (Bob) is 1, (BO
o) becomes 0.

The relationship between input and output as described above is shown in FIG. 3 as a truth table.

Next, a 4-bit station multiplier constructed by cascading the above unit circuits (1) to (5) will be described.

The highest unit circuit (1) is a circuit for this complement display. The sign bit of this complement representation (×4) is 1
When , the output (Boo) is O, (80,) is 1, and (not) is connected to (Bl) of unit circuit (2), so (Y) of unit circuit (2), i.e. output(
P, ) is always 1.

Unit circuits (2) to (5) are circuits that perform calculations on the numerical part, and (Y) outputs the multiplication results (P2) to (PS).
BOo) is connected to the input "A" of the next stage, and (BOt) is connected to the input rBI of the next stage. The multiplier is multiplied by the multiplier, and the horizontal 1 bit and the remainder 2 bits are output.

(P,) is the lowest remainder output, which is output every time the product is calculated. That is, (PI) is (Ps) ~ (P2)
If you add it to , it will be rounded off, and if you do not use (P,), it will be rounded down.

In the above embodiment, the case of 4 bits is shown, but the number of bits may be any number, and the unit circuit (1)
~(5) is composed of a combination of logic elements, then the second
The configuration is not limited to the one shown in the figure, and the multiplier may be any fixed multiplier regardless of the station.

Furthermore, in the above embodiment, the unit circuits (2), (3), (4), and (5) for calculating the numerical part are connected in cascade to each other, but it may be configured by combining other logic elements. You can also do that.

(Effects of the Invention) As explained above, this invention does not generate or add partial products, but instead configures a multiplier circuit by combining logic elements, thereby realizing multiplication using a fixed multiplier. This has the advantage that it is possible to simplify the process and obtain a high-speed multiplier.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a multiplier according to an embodiment of the present invention, FIG. 2 is a logic circuit diagram showing a unit circuit forming the multiplier in FIG. 1, and FIG. 3 is a unit circuit in FIG. 2. Figure 4 is a configuration diagram showing a conventional multiplier, Figure 5 is a truth table showing the input/output relationship of
The figure is a logic circuit diagram showing unit circuits constituting a conventional multiplier. (1), (2), (3), (4), (5)...Unit circuit, (x Otori), (x2), (Xs), (X,)...
Multiplicand input, (Pl), (P, ), (Pl), (P4)
, (Pg)... Multiplication result output. In each figure, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] A multiplier that outputs the result of multiplying a multiplicand input of multiple bits by a multiplier, characterized in that a multiplier circuit configured by a combination of logic elements and configured to calculate the result of multiplying the input multiplicand input and a fixed multiplier is provided. Multiplier to do.