JPS615616A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To expand an operation margin by using an ECL circuit for an FF circuit included in a digital semiconductor integrated circuit device formed of an NTL circuit. CONSTITUTION:A multistage logical gate circuit consisting of NOR gate circuits G1 and G2 and an inverter circuit IV is formed of the NTL circuit. The FF circuit consisting of NOR gate circuits G3-G6, on the other hand, is formed of the ECL circuit. Thus, the ECL circuit having a constant logical threshold value is used as the FF circuit instead of the NTL circuit, so deterioration in operation margin due to element variance, variance in source voltage, etc., is prevented. Consequently, the operation margin is expanded on the whole.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a semiconductor integrated circuit device, and can be used, for example, in a semiconductor integrated circuit device constituting a gate array or the like constituted by an NTL (non-threshold logic) circuit. It is related to effective technology.

[Background technology]

Conventional TTL (transistor transistor logic) or ECL (emitter complable logic)
Unlike the NTL circuit that refers to a threshold voltage and distinguishes between high level and low level, an NTL circuit that does not have a specific logic threshold has been proposed. The inventor's research has revealed that this NTL circuit has the following problems.

In other words, in an NTL circuit, the signal is amplified through multiple gate circuits, so the input-output transfer characteristics of the multiple gate circuits vary depending on the center voltage, as shown by the solid line in Figure 1. If the signals intersect, input levels higher than this intersection point are sequentially amplified and eventually converge at point A on the high level side. However, due to variations in element characteristics or variations in power supply voltage due to voltage drop due to distributed resistance in the power supply line, the intersection of the two transfer characteristics changes from near the center, as shown by the broken line in Figure 1. If it deviates, the level margin of the high level (point A side) will deteriorate in this example.

In logic gate circuits, multiple logic gates are configured in multiple stages, so even if there are variations in the above transfer characteristics,
Since the level is corrected by passing the signal through other logic gate circuits that also have variations, it does not pose much of a problem in practice.

However, since the flip-flop circuit performs the information storage operation through its positive feedback operation, an infinite loop is constructed of logic gate circuits having variations as shown in FIG. 1 above. For these reasons,
If a flip-flop circuit is constructed with an NTL circuit, its operating margin will be extremely deteriorated (NTL circuit).
Regarding the L circuit, see, for example, "Latest Electronic Device Encyclopedia J, Section 72, written by Genshiki Baba, published by Radio Gijutsusha on March 20, 1976."

[Purpose of the invention]

The purpose of this invention is to realize an NT that realizes an expanded operating margin.
An object of the present invention is to provide a semiconductor integrated circuit device including an L circuit.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

(Summary of the Invention) A brief summary of typical inventions disclosed in this application is as follows.

In other words, a flip-flop circuit included in a digital semiconductor integrated circuit device configured with an NTL circuit is
By configuring the semiconductor integrated circuit using L circuits, the overall operating margin of the semiconductor integrated circuit device is expanded.

〔Example〕

FIG. 2 shows a circuit diagram of an embodiment of an internal logic circuit in a semiconductor integrated circuit device according to the present invention. Each circuit element in the figure is formed on a semiconductor substrate such as single-crystal silicon of 1 (I!) by a known semiconductor integrated circuit manufacturing technique, although this is not particularly limited.

Although not particularly limited, a Noah (N
OR) The output signal of gate circuit G1 is passed to NOR gate circuit G2.
to one input of the . This NOAR game circuit G2 forms an output signal according to the above input signal and another input signal No. 2.Then, the inverter circuit IV
The output signal is supplied to other logic gates (not shown) through the gate. In this way, a logic gate circuit having a multi-stage configuration is composed of an NTL circuit.

On the other hand, although not particularly limited, NOR gate circuits d3 to G6
The flip-flop circuit FF configured by ECL
Consists of circuits. That is, although not particularly limited, the output signal of the NOR gate circuit Gl is used as the input signal, and the NOR gate circuit G3. Commonly supplied to one input terminal of G4. The above NOR gate circuits 03 to G501
A set signal S is commonly supplied to the two input terminals.

The inverted clock signal i can be completely supplied to the remaining 1 input terminal of the NOR gate circuit G3. Furthermore, the non-inverted clock signal CK is supplied to the other input terminal of the NOR gate circuit G5. One output signal of the NOR gate circuits 03 to G5 has a wired-OR configuration, and is supplied to one input terminal of the NOR gate circuit G6. The other output signal of the NOR gate circuits 03 to G5 is sent to another logic circuit (not shown) as an inverted output signal d of the flip-flop.

The remaining two input terminals of the NOR gate circuit G'6 are
Reset signals R1 and R2 are respectively supplied to the output terminals. The output signal of this NOR gate circuit G6 is the output signal of the NOR gate circuit G4. The signals are fed back to the remaining input terminal of G5, and the non-inverted output signal Q of the flip-flop is sent out from the positive output terminal of the NOR gate circuit G6.

The information holding operation of this flip-flop circuit FF is performed when the cent signal S, the reset signals R1 and R2, and the non-inverted clock signal CK are at logic "0", and when the inverted clock signal CK is set to logic "1", the NOR gate circuit G4 .G5 and 06
This is done by a positive feedback loop created by □ Figure 3 shows the N circuits that constitute the NOR gate circuit 01, etc.
T L circuit and E that constitutes the above NOR gate circuit 03 etc.
A circuit diagram of a specific example of a CL circuit is shown.
゛The NTL circuit consists of an input transistor Q1 arranged in parallel.
Resistors R1 and R2 are respectively connected to the commonly connected collector and emitter of ~Q3.

Then, the collector outputs of the transistors Q1 to Q3 made common are supplied to the base of an emitter follower output transistor Q4 to obtain an output signal. In addition,
When obtaining multiple output signals, the above output transistor Q4
However, a plurality of output transistors having a multi-emitter structure or having a common base and collector are used.

On the other hand, the ECL circuit is composed of the following circuit elements. A transistor Q8 is provided which is of a differential type with respect to the parallel type input transistors Q5 to Q7 and whose base is supplied with a reference voltage VBB as a logic threshold. A load resistor R4 is provided at the common collector of the transistors Q5 to Q7. Furthermore, a constant current source IO is provided between the common emitter and the power supply voltage terminal. When obtaining the NOR output of the signals from the common collector of the transistors Q5 to Q7 and the collector of the transistor Q8, the collector signal of the transistors Q5 to Q7 is transmitted to the base of the emitter follower output transistor Q9, and the output signal is output from the emitter. is sent. Note that, in the case of obtaining a plurality of output signals, an output transistor having a multi-emitter structure or a plurality of output transistors is provided in the same manner as described above. When the outputs of the plurality of ECL circuits are connected in a wired-OR configuration, only one of the load resistors R6 prepared for each of the plurality of ECL circuits is connected. This also applies to the NTL circuit described above.

〔effect〕

ill In the information retention operation, by using an ECL circuit with a fixed logic threshold instead of an NTL circuit as the flip-flop circuit that forms the infinite loop, deterioration of the operating margin due to element variations or power supply voltage variations can be prevented. can. This results in N
Since the cause of deteriorating the operating margin in the TL circuit can be removed, it is possible to obtain a semiconductor integrated circuit device with a significantly expanded operating margin as a whole.

(2) The above-mentioned Tll allows the operation margin to be expanded, so the yield of the product can be increased, so mass production can be improved, and as a result, the price can be significantly reduced. is obtained.

(3) According to the above (1), since the operating margin can be expanded, reliability can be improved.

(4) As a basic circuit, each circuit element constituting an ECL circuit as shown in Fig. 3 is prepared, and when used as an NTL circuit, it depends on whether or not to connect the differential transistor Q8. , an NTL circuit can be obtained, so switching can be easily performed using the master slice method. Therefore, it is extremely easy to mix an NTL circuit and an ECL circuit in one semiconductor integrated circuit, and there is no need to increase the number of special manufacturing steps. It is possible to obtain the following effects.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, the NTL circuit shown in FIG. 3 may be one in which the load of the emitter follower output transistor Q9 is divided into the base of the transistor Q8, and the output signal is level-shifted and fed back. For input signals supplied to the bases of input transistors Q5 to Q7, transistor Q
Since the output signal according to the above-mentioned input signal is fed back to the base of 8, it operates as an NTL circuit having no specific logic threshold. In this case, since the ECL circuit and the NTL circuit are composed of the same elements, there is no waste of elements and the NT
It is possible to improve the operational merge of the L circuit.

Further, the constant current source in the ECL circuit may be simply constituted by a resistor. Furthermore, transistor Q
A resistor may be provided at the collector of 8.

(Field of Application) The present invention can be widely applied to semiconductor integrated circuit devices such as gate arrays that include NTL circuits and are formed using a master slice method or the like.

[Brief explanation of drawings]

FIG. 1 is a characteristic diagram for explaining the operating margin of an NTL circuit, FIG. 2 is a circuit diagram showing an embodiment of an internal logic circuit in a semiconductor integrated circuit device according to the present invention, and FIG. FIG. 2 is a circuit diagram showing a specific example of an NTL circuit and an ECL circuit.

Claims (1)

[Claims] 1. A logic gate circuit configured with an NTL circuit, and an E
1. A semiconductor integrated circuit device comprising a flip-flop circuit configured with a CL circuit. 2. The semiconductor integrated circuit device according to claim 1, wherein the circuit function of the semiconductor integrated circuit device is formed by a master slicing method.