JPH01297728A - Microprogram start address generating system - Google Patents

Abstract

PURPOSE:To save the capacity of control storage and to reduce a load on a main data processor by providing storage for command analysis to output plural microprogram start addresses by a command held at a command register. CONSTITUTION:Command input 6 sent from the main data processor is fetched in the command register 10 by a slave data processor by a command input timing signal 8 sent simultaneously, and it is held until the next command input timing is inputted. A fetched command 3 retrieves the storage 11 for command analysis and outputs the microprogram start addresses 1 and 2. The microproram start addresses 1 and 2 outputted from the storage 11 for command analysis are selected at a selection circuit 12 by a selection signal 5, and become th microprogram start address 4.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to microprogram address control, and particularly to a microprogram start address generation method.

[Conventional technology]

Conventionally, this type of microprogram start address generation method includes a command register that holds commands sent from the main data processing device, and a command analysis that searches for commands in the command register and outputs one microprogram start address. The output of the command analysis memory was used as the microprogram start address.

[Problem to be solved by the invention] □" In the conventional dual microprogram start address generation method, only one microprogram start address is generated for one command sent from the main data processing device. Regarding a compound instruction that instructs multiple types of operations by a single command, either the compound instruction-specific microprogram is contained in the control memory, or the sequence of single instructions for the operations that constitute the compound instruction is processed by the main data processing device. convert and send the converted single instructions one by one,
A method had to be adopted in which the secondary data processing device processes the instruction as a single instruction, so that it appears as if a compound instruction has been processed from the perspective of the main data processing device. According to the above two methods, the former is
There are problems in that the number of microprogram steps increases and the control memory capacity must be increased, and the latter increases the burden on the main data processing device and does not improve the overall data processing ability. There is.

[Means to solve the problem]

The configuration of the microprogram start address generation method of the present invention is such that data sent from the main data processing device is
a command register that holds the command sent from the upper data processing device in a macro program start address generation circuit of a subordinate data processing device that processes according to a macro program specified by the command sent from the main data processing device; and an analysis memory for outputting a microprogram start address searched by a command in the command register, and a plurality of microprogram start addresses can be output from the command analysis memory by one command 1. It is characterized by a selection circuit that selects one of a plurality of microprogram start addresses in the command analysis memory, a counter that generates a selection signal for the selection circuit, and a counter update control circuit that controls updating of the address. It is characterized by being composed of.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of a microprogram start address generation circuit according to an embodiment of the present invention. In particular, two macroprogram start addresses are registered in the command analysis memory 1 for one command and output. FIG.

The subordinate data processing device captures the command input 6 sent from the main data processing device (not shown) into the command register 1o according to the command input timing signal 8 sent out at the same time, and holds it until the next command input timing. . The fetched command 3 searches the command analysis memory 11 and outputs the microprogram start addresses 1 and 2. Microprogram start addresses 1 and 2, which are output from the command analysis memory 11, are selected by the jy selection circuit 12 in accordance with the selection signal 5, and become the microprogram start address 4.

The selection signal 5 is the output of the counter 13, and the selection signal 5 is the output of the counter 13.
3, the update operation of which is controlled by the counter update control circuit 14. Normally, when the command sent from the main data processing device is a compound instruction consisting of two types of operations, the command analysis memory 1 contains a microprogram containing a single instruction for the first operation to be executed as microprogram start address 1. If the start address and the microprogram start address of the single instruction of the next operation to be executed are registered as the microprogram start address 2, the counter update value 7 is set to O by the command input timing signal 8. When set in the counter 13, the microprogram start address 1 of the operation to be executed first in the compound instruction is selected as the microprogram start address 4 for command 3, and execution is started as a single instruction operation.

Next, when the counter update value is inverted and set in the counter 13 by the data processing start timing signal 9 by the first step execution of the microprogram for the single instruction operation, the microprogram for the next single instruction to be executed starts. Microprogram start address 2 is selected as the address. Therefore, if the microprogram start address is used in the final step of the first operation, the next operation can be started without interruption after the first operation is completed.

As mentioned above, there is no need to prepare a dedicated microprogram for compound instructions that execute two types of operations, and
This allows execution without updating the command register. To terminate the microprogram, a stop counter is provided to generate a timing for stopping the program. Furthermore, by shifting the value of this stop counter so that it can be set freely, vector instructions etc. can be easily handled.

〔Effect of the invention〕

As explained above, the present invention provides microprogram start address generation for a secondary data processing device that processes data sent from a main data processing device according to a microprogram specified by a command sent from the data processing device. The circuit includes a command register that holds commands sent from the upper data processing device, and a command analysis memory that outputs a plurality of microprogram start addresses according to the commands held in the command register. a circuit for selecting one of a plurality of program start addresses outputted from the command analysis memory as an actual microprogram start address, a counter for generating a selection signal for the selection circuit, and a counter for updating the counter. By providing a counter update control circuit to control, complex instructions that execute multiple types of operations can be executed by preparing a single instruction microprogram for basic operations, without having to prepare a dedicated microprogram. This allows the capacity of the control memory to be saved, thereby reducing the amount of hardware. Furthermore, in order to execute a compound instruction, there is no need for the main data processing device to convert the compound instruction into a series of single instructions and have the slave data processing device execute it, which reduces the burden on the main data processing device. , which has the effect of improving overall data processing ability.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a microprogram start address generation circuit according to an embodiment of the present invention. 1... Microprogram start address (operation to be executed first), 2... Microprogram start address (operation to be executed next), 3...
・Command to be executed, 4...Microprogram start address (used for actual data processing), 5...
... Selection signal, 6 ... Command manual input (sent from the main data processing device), 7 ... Counter update value, 8 ... Command input timing signal (sent from the main data processing device), 9...
...Data processing start timing signal (first step of microprogram of main data processing device), 10
...Command register (holds commands sent from the main data processing device), 11...
・Command analysis memory, 12...Selection circuit, 1
3...Counter, 14...Counter update control circuit. −0−Representative Patent Attorney Susumu Uchihara−186”−

Claims (1)

[Claims] In a macro program start address generation circuit of a subordinate data processing device that processes data sent from a main data processing device according to a macro program specified by a command sent from the main data processing device, the main data It has a command register that holds commands sent from the processing device, and an analysis memory that outputs the microprogram start address after being searched by the command in the command register. a selection circuit that outputs a plurality of microprogram start addresses and selects one of the plurality of microprogram start addresses in the command analysis memory; a counter that generates a selection signal for the selection circuit; A microprogram start address generation method comprising: a counter update control circuit for controlling update of the address.