JPH01298596A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To reduce power consumption by operating only a small block of a selected memory cell at the time of read/write operation, and at the time of refresh operation, simultaneously operating plural blocks correspondingly to the regulated number of refresh cycles. CONSTITUTION:At the time of read/write operation, a refresh control circuit 103 selects one of two memory cell arrays 104, 105 by a selection signals phiB1, or phiB2 to drive its line decoder 101 (102) and a sense amplifier 106 (107). In the refresh mode, the refresh operation of all the memory cells is completed by the regulated number of cycles, so that it is necessary to simultaneously drive the two memory cell arrays 104, 105 and the circuit 103 activates both the signals phiB1, phiB2 to drive the line decoders 101, 102 and the sense amplifiers 106, 107 in both the blocks. Consequently, power consumption due to the charge of a bit line can be sharply reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and more particularly to a refresh method for a dynamic random access memory device (hereinafter referred to as RAM).

[Prior Art] A refresh method for a dynamic RAM (hereinafter abbreviated as DRAM) is defined in its standard. For example, in the case of IM DRAM, if the row address is changed every 8ms and refresh is performed for 512 cycles,
It is guaranteed that all memory cells have been refreshed and their information is retained. Therefore, the inside of DRAM is
It was configured so that all memory cells were selected internally by simply selecting the 5120th row address externally.

This configuration will be explained using FIG. 4 using an IM DRAM as an example. Memory cells 401 are arranged in a two-dimensional matrix and are placed at the intersections of word lines selected by row decoder 402 and bit lines selected by column decoder 403. Since there are 512 refresh cycles, the configuration includes 512 row decoders that selectively drive word lines, and 2048 sense amplifiers that perform refresh operations and amplify read signals from column decoders and memory cells. The address signal that is input by an external person is
Row address, which is the refresh address, Xo-X8
and column address, YO to Y10 are the respective addresses.
It is input to a decoder where it is amplified by a buffer.

Next, the operation will be explained. The internal operations are exactly the same during read/write and refresh. first,
When a row decoder 402 corresponding to an external address is manually selected, 2048 memory cells connected to that word line are simultaneously selected and simultaneously refreshed by sense amplifiers connected to each bit line. Therefore, if all 512 row decoders are selected, 1
Refreshing of all M-bit memory cells is completed.

In the read/write operation, the column decoder 403 then selects a bit line to complete the selection of one bit of memory cell.

[Problems to be Solved by the Invention] As mentioned above, DRAM must complete its refresh in a specified number of cycles, so even though the memory cell selected externally is 1 bit, internally Many memory cells are selected at the same time and a refresh operation is performed.

In the case of the IM DRAM used as an example, internally there are 204
Eight bits of memory cells are simultaneously selected and refreshed. However, in a normal read/write operation, the memory cells selected are random, so the memory cells that are refreshed and refreshed at the same time are also random, and all the memory cells are not refreshed uniformly.

Therefore, even though many memory cells are refreshed during normal read/write operations, information retention in all memory cells cannot be guaranteed unless a completely independent refresh operation is performed. In other words, the refresh performed during normal read/write operations is wasted.

By the way, there are various problems with increasing memory capacity.
The biggest problem among these is the increase in power consumption. DRAM
In this case, refresh current accounts for the largest proportion of power consumption. Taking IM DRAM as an example, each bit line connected to a memory cell has a capacity of about 0.5 PF, and refreshing is performed by charging and discharging 2048 bit lines at the same time. Therefore, the power supply voltage 5
(2) If the operation cycle time is 260 ns, the current will be approximately 30 mA, which will account for half of the total current consumption.

In other words, during normal read/write operations, there is a problem in that a large amount of power is consumed for refreshing, which ends up being wasted.

[Differences of the Invention with the Prior Art] In contrast to the conventional correction methods described above, according to the present invention, only a small block containing selected memory cells is operated during normal operation, and a specified block is not operated during refresh operation. Multiple blocks are configured to operate simultaneously so that refresh can be completed in the specified number of cycles.

[Means for Solving the Problems] In the semiconductor memory of the present invention, the entire semiconductor memory is divided into small blocks, and during normal read/write operations, only one small block containing a selected memory cell is operated to reduce consumption. The power consumption is reduced, and during a refresh operation, a plurality of blocks are configured to operate simultaneously corresponding to a prescribed number of refresh cycles.

[Example] Father-in-law of Natsume FIG. 1 is a block diagram showing a first embodiment of the present invention.

In this example, the whole is divided into two for the sake of simplicity, but the same method can be applied to further divisions. The larger the number of divisions, the greater the effect of reducing power consumption, but the complexity of control also increases, so it is not appropriate to increase the number of divisions unnecessarily.

The overall configuration is similar to the conventional example explained in FIG. 4, but the difference is that since it is divided into two, there are two identical row decoders 101 and two identical row decoders 101, and two identical row decoders 102, for a total of 1024 decoders. Further, in order to control the division, there is a refresh control circuit 103 that operates using the most significant digit φYIO of the column address and a refresh signal φREF.

First, normal read/write operations will be explained.

Since it is not in the refresh mode, the refresh control circuit 103 responds to the input external address Y10.
One of the two memory cell arrays 104 and 105 is selected by selection signals φB1 and φB2, and the block 104 (10
5) Row decoder 1θ1 (102) and sense amplifier 1
06 (107) is operated. The unselected block 105 (104) does not consume power because the row decoder 102 (101) and sense amplifier 107 (106) do not operate.

Next, the case of refresh operation will be explained. In refresh mode, in order to complete refresh of all memory cells in a specified number of cycles, two memory cell arrays 1
04 and 105 must operate simultaneously, the refresh control circuit 103 activates both φBl and φ82 by φREF, regardless of φYIO, and operates the row decoders 101, 102 and sense amplifiers 106, 107 of both blocks.

The refresh signal may be input as an external signal, or it may be input as an external signal, or it may be ROR (RAS), which is the standard for DRAM.
0NLY REFRESH) or CBR (C
This may be determined and generated internally depending on the AS BEFORE RAS) mode.

The problem with refresh operation is that it consumes a lot of power, and since a large current flows in a short period of time, it causes a large potential drop due to the resistance of wiring such as the power supply and GND, making the circuit operation unstable. Sometimes it happens. According to the first embodiment of the present invention, the current in read/write operations decreases, but the current in refresh operations does not change. This means that as long as DRAM requires refreshing,
Although this is an unsolvable problem, it is possible to reduce the instantaneous peak current value and reduce the influence of potential drop due to wiring resistance. Since the total current value remains unchanged, the operating time of the sense amplifier can be lengthened to reduce the peak current, but this will slow down the read/write speed. According to the present invention, since the current for reading and writing is small, it is only necessary to slow down the operating speed during the refresh operation.

FIG. 2 is a block diagram of a second embodiment in which a function of slowing down the operation speed only during the refresh operation of the first embodiment is added, and FIG. 3 is a circuit diagram of the sense amplifier portion thereof.

Compared to FIG. 1, FIG. 2 shows a sense amplifier 201,
In order to control the operating speed of 202, a signal φR9E is added. In the second embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and the explanation thereof will be omitted.

The sense amplifier circuit shown in Figure 3 uses two types of cross-connected N-channel and P-channel transistors.
It is composed of an O5 type flip-flop. Further, the commonly connected sources of each are connected to the signal lines φSN and φSP. Although 6 is omitted in the figure, this signal line is common to a plurality of sense amplifiers. Transistors Ql-Q4, which connect these signal lines to the power supplies of VCC and GND, respectively, are connected to the refresh control circuit 20.
Refresh signal φR9E from 3, its reverse transmission signal φR
5E, a block selection signal φB1, and its reverse transmission signal φB1.

Here, the operation of the sense amplifier will be briefly explained.

Before the start of operation, the bit line, φSN, and φSP are all VC.
It is precharged to an intermediate potential between the two power supplies C and GND. When a read operation begins, a memory cell signal first appears on one bit line, and a difference signal is generated on the pair of bit lines. Next, φSN.

Amplification is performed by moving φSP with respect to each power supply. Since the current flowing through the sense amplifier is determined by the speeds of φSN and φSP, the peak current can be reduced by moving them slowly.

In the example shown in the figure, in read/write operations, the operation speed is determined by Ql and Q3 driven by block selection signal φB1.
In the refresh operation, Q2. Q4
It is determined by Therefore, if Q2°Q4 is made smaller than Ql and Q3, the refresh speed will be slowed down and the peak current can be reduced.

[Effects of the Invention] As described above, according to the present invention, only a small block including a selected memory cell operates during normal read/write operations, so power consumption due to bit line charging is greatly reduced. .

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the first embodiment of the present invention, Fig. 2 is a block diagram of the second embodiment, Fig. 3 is a circuit diagram of the sense amplifier circuit portion of the second embodiment, and Fig. 4 is a conventional circuit diagram. FIG. 2 is a block diagram illustrating an example. 101, 102・Conflict・Row decoder, 103.203
...Refresh control circuit, 104.105...φ
・Memory cell array, 106.107゜201.202...Sense amplifier, Xo-X
8...External input line address, YO~YIO・
...External input column address, φREF...
・Refresh signal, φBl, φB2...Block selection signal, φR5E...Sense amplifier drive signal during refresh, φSP, φ5N--Sense amplifier common node signal, Ql
-Q4...Transistor. Patent applicant Kiyoshi Kuwai, agent for NEC Corporation and patent attorney - Figure 1

Claims (4)

[Claims] (1) In a dynamic semiconductor memory device configured by dividing the memory cell array into small blocks, when performing read/write operations, only the small blocks containing selected bits are selectively operated. A semiconductor memory device characterized in that, in a refresh operation, a plurality of small blocks operate simultaneously and refresh of all memory cells can be completed in a prescribed number of cycles. (2) In read/write operations and refresh operations,
2. The semiconductor memory device according to claim 1, wherein the operating speed of a sense amplifier that performs a refresh operation is changed to reduce a peak current value. (3) The semiconductor memory device according to claim 1 or 2, wherein switching between read/write operations and refresh operations is controlled by ROR mode or CBR mode. (4) The semiconductor memory device according to claim 1 or 2, further comprising an external signal terminal for controlling switching between a read/write operation and a refresh operation.