JPH02177192A - Large capacity dynamic type semiconductor memory - Google Patents

Abstract

PURPOSE: To decrease an access time and to improve an access efficiency by increasing the number of bits composing row addresses larger than the number of bits composing line addresses. CONSTITUTION: A memory cell array M is divided into two blocks Ma and Mb, and each of the memory array blocks Ma and Mb is divided into eight blocks M1-M8 and M9-M16 respectively. Namely, a memory cell of 16 M bits is totally divided into 16 blocks, and each of the memory cell array blocks M1-M16 has memory cells arranged as 256 lines × 4K2<12> . As a result, one of 256 lines can be selected by 8-bit line address and data field of 64K bits can be accessed by 16 bit row address. Consequently, a data size for one page can be expanded to 64k bits, and data can be written/read in/from the memory cells at a higher speed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a large-capacity dynamic semiconductor memory device, and particularly to a configuration for performing multi-bit serial access mode operations such as page mode and static column mode at higher speed. Regarding.

[Prior art] Semiconductor random access memory (RAM) includes static RAM (SRAM) and dynamic RAM.
CDRAM). The major difference between SRAM and DRAM is that DRAM requires a refresh operation to periodically rewrite memory cell data.

In an SRAM, normally, a row address and a column address are applied at the same time, and the row and column addresses are taken into the device by a chip enable signal CE to access a selected memory cell.

On the other hand, in DRAM, 4K (2”) DR in 1974
After AM, a configuration has been adopted in which row addresses and column addresses are time-division multiplexed and applied to the same address input terminal. The address multiplex method in this DRAM will be briefly explained.

FIG. 2 is a diagram showing the arrangement of external signal output bin terminals of a DIP (dual cost in-line) package of an LM (22°) DRAM. In FIG. 2, pin numbers are shown within square frames. In IMDRAM, 10
Bit row address signals AO-A9 and 10-bit column address signals AO-A9 are applied to pin numbers 5 to 8 and pin numbers 10 to 15 in a time division multiplexed manner. The timing at which the row address and column address applied to this address input terminal are taken into the device is determined by the row address strobe signal RAS applied to pin number 3 and the row address strobe signal RAS applied to pin number 16.
A column address strobe signal CAS is applied to the column address strobe signal CAS. That is, the row address strobe signal R
When AS falls to the "L" level, the device is activated and the row address is taken into the device. On the other hand, when the column address strobe signal CAS falls to the 'L level, the column address signal is taken into the device. Data write and read operations of the semiconductor memory device are performed using the write enable signal WE.
(applied to pin number 2). That is, when the write enable signal qWE is at "H" level, this indicates that this semiconductor memory device is in a read operation, while when the write enable signal WE is at "L", this indicates that this device is in a data write operation. Show that. Input data D
I is applied to pin number 1, and output data DO is output from pin number 17. Data write timing is signal W
This is given by the timing of falling of the signal E and the signal CAS to the "L" level, whichever is later.

The data read timing is such that the signals CAS and WE are at the "H" level, and valid data is read out after a predetermined period of time has elapsed after the signal CAS falls to the "L" level.

As mentioned above, for example, in the case of IMDRAM, a 20-bit address signal is required, but this 20-bit address signal is divided into a 10-bit row address signal and a 10-bit column address signal, and this row address signal By time-division multiplexing and column address signals and applying them to the address input bin, a 20-bit address signal can be input manually using a 10-bit pin terminal, which reduces the need for address signals as the capacity of semiconductor memory devices increases. Even if the number of bits increases, the increase in the number of pin terminals can be suppressed.

Next, the internal structure of a conventional IMDRAM will be schematically explained with reference to FIG.

Referring to FIG. 3, each IMDRAM has 256 rows (2
8) Two memory cell array blocks la and l having memory cells arranged in rows and columns of 2K (2”) columns.
Contains b. Memory cell array blocks la and lb each provide a storage capacity of 512 bits, totaling 1M
Gives storage capacity in bits.

Row address signal AO applied externally to select memory cells in memory cell array blocks la and lb
A row address latch 3 receives internal row address signals RAO to RA9 and latches them in response to a signal RAS, and receives a column address signal AO to A9 from the outside applied via an address input terminal 2. , latches in response to signal CAS and outputs internal column address signal CAO~
Column address latch 4 that generates CA9 and internal row address signals RAO to RA7 from row address latch 3
row decoders 5a and 5b which select one row out of 256 rows, internal column address signals CAO to CA9 from column address latch 4 and row address latch 3.
Column decoders 6a and 6b are provided for receiving the most significant internal row address signal RA9 from column 2 and selecting one column from columns.

Internal row address signal RAS from row address latch 3
is used as a block selection address, and only one of the memory cell array blocks la and lb is enabled.

In order to input and output data to and from memory cells selected by external row and column address signals AO to A9,
A sense amplifier detects and amplifies information held in memory cells connected to one row selected by row decoders 5a and 5b, and selects 1-bit memory cell in response to column decode signals from column decoders 6a and 6b. ■1
An I10 gate is provided which connects to the 0 buffer 7. In FIG. 3, the sense amplifier and I10 gate are shown in one block 8a, 8b.

A RAS system receives an external row address strobe signal RAS applied from the input terminal 11 and generates internal control signals related to the row selection operation in order to define data write/read, row selection, and column selection operations of the semiconductor memory device. A CAS system that generates an internal control signal related to column selection in response to a column address strobe signal CAS applied from the outside via the input terminal 13 of the RAS system clock clock generator 12 and an internal control signal of the RAS clock clock generator 12. a clock generator 14; an R/W clock generator 15 that generates a clock signal that provides data write and read operation timing in response to an internal control signal from the CAS system clock generator 14; An R/W control circuit 16 is provided which responds to the clock signal from the I10 buffer 15 and activates either the input section or the output section of the I10 buffer 7 in response to a write enable signal WE applied from the outside.

Here, in FIG. 3, address signal AO is input to input terminal 2.
It is assumed that input terminal 2 has a width of 10 bits. Next, the operation will be briefly explained.

First, a 10-bit row address signal AO to A9 is applied from the outside via the address input terminal 2.

The row address latch 3 latches the row address signal applied to the address input terminal 3 in response to the transition of the signal RAS to the "L° level," and outputs the internal row address signals RAO to RA.
Generates 9. This 10-bit internal row address signal RA
8-bit internal row address signal RAO of O-RA9
~RA7 is applied to row decoders 5a and 5b. A 1-bit internal row address signal RAS is used as a block selection address. Therefore, row address signal RA
Only one of memory cell array blocks 1a and 1b is enabled by S. Now, suppose that memory cell array block 1a receives internal row address signal R
Assume that it is selected by AS. In this case, the row decoder 5a is activated, decodes internal row addresses RAO to RA7, selects one row out of 256 rows of the memory cell array block 1a, and sets the potential of the word line defining this one row to "H". ``Raise the level. Thereafter, the sense amplifier included in block 8a is activated, and the information of the memory cell connected to this selected word line is sensed and amplified.

Next, the column address signal AO~
A9 is applied to column address latch 4. Column address latch 4 receives column address strobe signal CAS
The 10-bit address signal given in response to is taken in as a column address signal and internal column address signals CAO~
Generates CA9. Column decoder 6a decodes these 10-bit internal column address signals CAO-CA9 and 1-bit most significant row address signal RA9, and selects one of the columns. The memory cells connected to this selected column are connected to the I10 buffer 7 via the 10 gate included in the block 8a. As a result, data is written into or read from the memory cell selected according to the state of write enable signal WE.

Here, both the row address latch 3 and the column address latch 4 receive external address signals AO to A9 at the same time.
is applied via the input terminal 2, and the row address latch 3 and column address latch 4 each take in the signal given as a trigger signal by the falling edge of the control signal to the "L° level," and output the row address and column address. Separating addresses.

A data field formed by memory cells connected to one row selected by one row address (one set of row address signals AO to A9) as described above is called a "page". Signal RAS without change
Toggle the signal σx1 while keeping it at "L level,"
For each toggle, take in the column address from the outside,
The operation of selecting data within this page is called "page mode 1." In this page mode operation, it is not necessary to apply both a row address and a column address as in the normal 1-bit operation mode. After applying the row address, you can access the memory cell by toggling the column address strobe signal CA by simply changing the column address, so you can access the memory cell faster than in normal mode. Page mode, which is such a high-speed serial access mode, and address multiplexing method to reduce the number of pin terminals are still used in DRAM as standard technology. Various improvements have been proposed to speed up the row selection operation using the row address and the column selection operation using the column address. A nibble mode in which a 4-bit memory cell is selected and accessed by sequentially toggling the signal CAS, or a nibble mode in which a 4-bit memory cell is accessed by sequentially toggling the signal CAS, or, for example, a 2-stage shift register is provided and the connection between this shift register and the selected page is selected. There is a method adopted in video RAMs and the like in which data is exchanged between the two, and input and output of data to and from the outside is performed via a shift register.

On the other hand, even if semiconductor memory devices are highly integrated to increase their capacity, there is a limit to the sensing ability of sense amplifiers for detecting and amplifying signal potentials on bit lines (column selection lines). The sense amplifier cannot accurately detect data on the bit line when the ratio of the bit line capacitance to the memory cell capacitance exceeds a value. The sense margin of this sense amplifier will be explained with reference to FIG.

FIG. 4 is a diagram schematically showing the configuration of one column of a memory cell array block. In FIG. 4, the bit lines constitute folded bit lines, and a bit line BL and a complementary bit line BL are arranged in pairs and parallel to each other. bit line BL,
256 word lines WLI to WL intersect with BL
256 and two dummy word lines DWLI and DWL2.
is provided.

A memory cell MC is provided at one of the intersections between one word line and a pair of bit lines. That is, the bit line BL is connected to the word lines WLI, WL3 (not shown), . . .
The complementary bit line BL has a memory cell MC at the intersection with the word lines WL2, . . . WL256. A dummy cell DM is provided at the intersection of the dummy word line DWL1 and the bit line BL. A dummy cell DM is provided at the intersection of dummy word line DWL2 and complementary bit line BL. This dummy cell DM is Vc
c/2 (“H” level information stored in the memory cell is Vc
C level) and provides a reference potential during the sensing operation of memory cell data.

The memory cell MC is composed of a memory capacitor C that stores information in the form of charge, and a transfer gate transistor T that is turned on in response to a word line potential and connects the memory capacitor C to a corresponding bit line.

An equalize-precharge circuit PE is provided to charge and equalize the potential on the bit lines BL, BL to a predetermined potential V[1 during standby of the semiconductor memory device.

In order to detect and amplify the signal potential difference on the bit lines BL, BL, a sense amplifier SA is activated in response to a sense amplifier activation signal φ0 and differentially amplifies the signal potential on the bit lines BL, BL. is provided.

In order to access a memory cell, bit lines BL and B are activated in response to column decode signals from column decode 6 to .
I10 gate transistors TRI and 'rR1' are provided to connect L to data input/output buses ■10 and ilo, respectively. Next, the read operation of memory cell data will be briefly explained with reference to FIG.

Assume now that word line WLI is selected. Word line WL
When 1 is selected, the transfer gate transistor T of the memory cell MC becomes conductive, and a signal potential corresponding to the information held by this memory cell MC appears on the bit line BL. On the other hand, at this time, dummy word line DWL2 is selected, and the information held by this dummy cell DM is transmitted onto complementary bit line BL. After the signal potential is present on the bit lines BL, BL, the sense amplifier SA is activated in response to the sense amplifier activation signal φO, and further amplifies this signal potential difference. When the signal potentials on the bits MBL and BL are determined by the sense amplifier SA, the column decode signal from the column decoder 6 turns on the I10 gate transistor TR1°TR1', and the bit lines BL and BL are connected to the data input/output bus I10. Connected to I10.

As a result, data is written or read.

Now, the bit line BL when this sense amplifier SA detects
, BL will be considered.

The memory cell MC stores a charge corresponding to the signal potential V, l of m7'' level in its memory capacitor, while the dummy cell DM has the reference potential ■, (usually ■).

/2) is accumulated. In addition, bit lines BL, B
Assuming that the capacitance at which L becomes H is CB, and the capacitance value of the memory capacitor is Cs, the potential difference between the bit lines BL and BL when selecting a word line is (VB aCB +Cs V
n ) / (Ca + C5) (Ve ” Ca + C
sv, )/(C[1+C3)=Cs (VHVe)
/ (CB 10Cs) = (Vn Ve) /
(1+Ca/Cs)~(VIIVi)/(C
a/Cs). As can be seen from the above equation, in order to operate the sense amplifier SA as early as possible and ensure the sensing operation, C
B/Cs should be made as small as possible. However, when a large number of memory cells are connected to a bit line, the bit line capacitance Ca increases due to factors such as the parasitic capacitance associated with the memory cells and the length of the resist line. The more the capacitance C5 of the memory capacitor becomes smaller. Therefore, this ratio Ca/C
s becomes large. In normal DRAM,
This ratio Ca/Cs has a value of about 10 to 15, and if it is made larger than this value, the signal potential difference that appears between the bit lines becomes small, making it impossible to perform a sense operation reliably. I can't.

Normally, in a large-capacity ffiDRAM, the capacitance value of a memory capacitor is about 40 fF to 50 fF, so the bit line capacitance fl Ca cannot be made larger than 400 to 750 fF.

In 4MDRAM and 16MDRAM, the bit line capacitance e is set to about 350 to 400 fF.

On the other hand, if 128 memory cells are connected to the bit line,
The bit line capacitance EI Ca is approximately 500 fF. Therefore, the maximum number of memory cells connected to one bit line is about 128, and the maximum number of memory cells connected to one column, that is, bit line BL and complementary bit line BL, is 25.
There will be 6 pieces.

Due to the above-mentioned limitations, for example, 16 Mbit DRAM
In this case, the number of word lines is 256, and the number of sense amplifiers is 64 (column 64). Furthermore, when applying an address signal using the conventional address multiplex method described above, the number of bits of the row and column addresses is 12 each.
Becomes a bit.

The data field that can be accessed with a 12-bit column address is 2+2 or 4 bits; the remaining 60 bits cannot be accessed. In other words, one page has 4 bits.

On the other hand, since it is possible to access 256 word lines with an 8-bit address signal, the 8-bit row address signal of the 12-bit row address signal is used to specify the word line, and the remaining 4 bits are used to specify the word line. You must specify the data field with .

Therefore, in a 16M bit DRAM, a 16M bit memory array is divided into 16 1M bits as shown in FIG.
It is divided into bit blocks (256 rows x 4 columns), and one of the 16 blocks is designated by the remaining 4 bits of the row address signal. That is, as shown in FIG. 5, the 8-bit internal row address signal RAO
~RA7 selects one of the 256 word lines in each block, and the remaining 4-bit row address signals RA8~RAII selects and enables only one of the 16 blocks. condition. At this time, the remaining 15 blocks remain disabled. Access is made to the data field of the page selected by the 12-bit column address in the selected 1M-bit memory cell array block.

[Issue 8 to be solved by the invention] As mentioned above, in the case of the conventional 16 Mbit DRAM, the memory array is divided into 16 blocks, and one row address supply can access one of these 16 blocks. 1
Only one memory cell block is selected and made accessible. Therefore, when accessing all 16 memory cell blocks, it is necessary to supply the row address 16 times, resulting in a disadvantage that the overall access time becomes longer. That is, for example, 16 Mbit D
When a RAM is used as a video memory for storing image data, 16 Mbits may be required for one field depending on the bit width of the image data, the number of pixels on one horizontal scanning line, etc. In such a video memory, writing and reading of image data is, for example, 4fc.
Alternatively, it is necessary to perform the process at a high speed of 8fc (fc: color subcarrier frequency). However, in conventional 16 Mbit DRAM, in order to access all blocks, it is necessary to supply the row address 16 times even if page mode is used, which is a high-speed access mode, and data can be written and read at high speed. become unable to do so. That is, in video memory, one horizontal scanning line is made to correspond to one row of a memory cell array, but there is a problem in that data writing and reading during one horizontal scanning period cannot be performed at high speed. occurs.

Furthermore, in the conventional 16M bit DRAM mentioned above,
The data size of one page is 4 bits, and DRAM
Depending on the usage, the data size of this page may cause problems.

Additionally, DRAM requires periodic refresh operations. To refresh all the memory cells of a 16 Mbit DRAM, 212 refresh cycles (12 bits of row address) are required, which increases the time required to refresh the memory cells. In this refresh operation, one row of memory cells is refreshed in one refresh cycle according to the refresh address, but it takes 16 times to refresh one row of memory cells in all blocks using the same refresh address. A refresh operation is required. Since external access is prohibited during this refresh operation, external devices such as a CPU (Central Processing Unit) are in a standby state during this time, resulting in a problem that memory access efficiency is reduced.

An object of the present invention is to provide an Omiya fiDRAM that eliminates the drawbacks of the conventional Omiya ffiDRAM described above, further reduces access time, and further improves access efficiency.

Another object of the present invention is to provide an Omiya file with expanded page data size and faster access.
The purpose is to provide iDRAM.

Still another object of the present invention is to provide a pseudo-static RAM (PSRM) that has improved access efficiency and can be externally accessed even during refresh operations.

Still another object of the present invention is to provide a large-capacity DRAM having a configuration in which various operating modes of the DRAM can be specified without adding external pin terminals.

[Means for Solving the Problems] A large-capacity dynamic semiconductor memory device according to the present invention includes a memory cell array divided into a plurality of blocks;
means for selecting one word line from each of the plurality of memory cell array blocks in response to an externally applied row address; and configuring at least one column from the memory cell array in response to an externally applied column address. The number of bits constituting the row address is smaller than the number of bits constituting the column address.

A large-capacity dynamic semiconductor memory device according to another aspect of the invention configures a column address by converting the number of bits forming a row address to a row address and a column address given in a time-sharing manner through a common address input terminal. It is less than the number of bits.

Further, the large-capacity dynamic semiconductor memory device according to the present invention is provided between adjacent blocks of the plurality of memory cell array blocks, and after a predetermined delay time has elapsed after the word line in the previous block is selected, the word line in the subsequent block is selected. means for activating the activated word line.

Still another large-capacity dynamic semiconductor memory device according to the present invention includes a latch means for latching a signal potential on each column in each column of a memory cell array, and a latch means that latches a signal potential on each column in each column of a memory cell array, and latches the latch means when the operation of a sense amplifier in a corresponding memory cell block is completed. The latch means includes means for electrically isolating each column from each other, and means for connecting the latch means to the data output bus in response to a column selection signal from the column selection means.

Further, in the large-capacity dynamic semiconductor memory device according to the present invention, row addresses and column addresses are applied through a common address input terminal in a time-division multiplexed manner, and the remaining address inputs are applied at the same timing as the row address application timing. The device includes means for receiving an operation mode designation signal applied to a terminal, and means for operating the DRAM in a predetermined operation mode based on the operation mode designation signal.

[Operation] In the above configuration, the number of bits making up the row address is smaller than the number of bits making up the column address. For example, in the case of a 16 Mbit DRAM, 24 bits are required for the address, but 8 bits of this 24-bit address signal are used as the row address, and the remaining 1 bit is used as the row address.
6 bits are used as column address. As a result, one row out of 256 rows can be selected using an 8-bit row address, and a 64-bit data field can be accessed using a 16-bit column address.

As a result, the data size of one page can be expanded to 64 bits, and data can be written and read from memory cells at higher speed.

In addition, 64 columns of memory cells are connected to one row, and the 64 columns are connected to each other.
Sense amplifiers are connected corresponding to the columns. Therefore, when the sense amplifiers of bits 64 and 64 are operated simultaneously, the peak current flowing during the sensing operation increases, causing fluctuations in the substrate potential and increasing current consumption. However, due to the word line potential transmission means provided between adjacent memory cell array blocks, the word line selection or activation timing in each memory cell array block is different for each block, and the sense amplifiers in each block are also at different timings. Since the current is activated by , the peak current during sensing operation can be dispersed and reduced.

There are 64 latch means provided between each sense amplifier and the data output bus, and after the sense operation is completed, they are electrically separated from each column, so each memory cell array block is refreshed. At the same time as the operation is performed, each latch means can be accessed from the outside using a column address, and a PSRAM can be realized.

In addition, the data size of one page has been expanded, and although the RAS access time, that is, the time required from applying a row address to accessing a memory cell, may be somewhat longer than in conventional DRAM, this page data size will increase. Therefore, the CAS access period (the time required from when a column address is given until accessing a memory cell) is shortened, and the overall access time can be reduced.

Furthermore, since the configuration is such that the operation mode designation signal is applied to the remaining address input terminals in parallel with the application of the row address, the DR
Various required functions of AM can be realized.

The objects and other objects and features of the invention will become more apparent from the following detailed description of embodiments of the invention with reference to the accompanying drawings.

[Embodiment of the Invention] FIG. 1 is a block diagram showing the overall schematic configuration of a large-capacity dynamic semiconductor memory device which is an embodiment of the present invention, and the configuration of a DRAM with a storage capacity of 16 Mbits is shown as an example. It will be done.

Referring to FIG. 1, memory cell array M is divided into two blocks Ma and Mb. Each memory cell array block Ma, Mb is divided into eight blocks M1-M8 and M9-M16, respectively.

In other words, a 16 Mbit memory cell has a total of 16
divided into blocks. Each of memory cell array blocks M1-M16 has memory cells arranged in 256 rows and 4K (2+2) columns.

When each column in each memory cell array block has a folded bit line configuration, a bit line and a complementary bit line are arranged in pairs corresponding to one column. Each memory cell array block Ma, Mb has a memory cell array block M.
Row decoder 50 to select one row from M1 to M16.
a and 50b are provided. Row decoder 50a responds to 8-bit internal row address signals RAO-RA7 from row address latch 30 to select memory cell array block M.
One word line is selected from each of M1 to M8. Row decoder 50b selects one row, ie, one word line, from each of memory cell array blocks M9-M16 in response to an 8-bit internal row address from row address latch 30. As will be clearly shown later, in memory cell array block Ma, memory cell array blocks M1 to M
A word line is commonly provided at 8. Similarly, in memory cell array block Mb, one word line extends across memory cell array blocks M9 to M16. Therefore, the row decoder 50a.

50b has 256 outputs, and this row decoder 50
a, 50b outputs to memory cell array blocks M1~
One word line is selected in each of M16.

Each of memory cell array blocks M1 to M16 includes a sense amplifier for detecting and amplifying selected memory cell information, a latch means for latching data sensed and amplified by the sense amplifier, and an internal column address from a column address latch. Blocks 81-B16 are provided which include a column decoder for selecting a corresponding column in response to a signal, an I10 gate for connecting the column selected at the column decoder output to a data output bus, and the like. This block 81-B
An example of the specific configuration of No. 16 will be described later.

Further, each of memory cell array blocks M1 to M16 is provided with error detection and correction (FCC) circuit blocks E1 to E16 for detecting and correcting errors in the memory cell array block during operation.

Furthermore, in order to reduce the peak current during sensing operation, a repeater R1 is installed between adjacent memory cell array blocks to delay the selected word line potential by a predetermined delay time and transmit it to the subsequent memory cell array block.
~R14 is provided.

A row address latch 30 receives a row address signal AO-A7 applied through an address input terminal 20 and generates 8-bit internal row address signals RAO-RA7 in order to select a row of memory cell array blocks Ma and Mb.
is provided. The row address latch 30 is connected to the input terminal 11
External row address strobe signal R applied via
The AS defines its operation timing.

In order to select a column from memory cell array blocks Ma and Mb, 16-bit internal column address signals CAO-CA16 are generated in response to signal CAS upon receipt of column address signals AO-A15 applied via address input terminals 20. A column address latch 40 is provided. Column address strobe signal CAS is applied via input terminal 3. Of the 16-bit column address signals from the column address latch 40, 14-bit internal column address signals are applied to the column decoders included in blocks 81 to B16, and the remaining 2-bit column address signals CAO, C
AI is applied to a selector 62 that defines the input/output data pit width.

The address input terminal 20 has 16 input bins set to H, and receives a column address and an 8-bit row address through the 16 input bins.

The remaining 8-bit address input bins, which are unused when a row address is applied, are supplied with a control signal that defines the internal operation of the DRAM, and is supplied to the control signal latch 70. Control signal latch 70 latches a signal applied in response to row address strobe signal RA from input terminal 11, and applies a corresponding operation mode designation signal to mode control circuit 60. In the above configuration, the operation mode designation signal and the row address signal are simultaneously applied to the address input terminal 20, and then the column address signal AO-A15 is applied to the address input terminal 20 in a time-sharing manner.

In order to refresh the DRAM, it is activated in response to a refresh instruction signal from the mode control circuit 60 to generate a refresh address and apply it to the row address latch 30, as well as to each of the error detection/correction blocks E1 to E16. A refresh counter 61 is provided to apply a start signal H/V to the refresh counter 61. FCCCC
Each block-E16 has a refresh counter 61
The error detection/correction operation is performed in response to the control signal H/V from the controller.

Mode control circuit 60 generates a corresponding internal operation designation signal in response to an operation mode designation signal from control signal latch 70, and also responds to signal RAS/CAS applied via input terminal 11.13. Detects presence or absence of refresh operation.

Further, in the above-described configuration, when the operation mode designation signal applied via the address input terminal 20 is a signal specifying the data output width, the mode control 60 transmits the signal specifying the output data pit width to the selector 62. and applied to the I10 buffer 63. In the configuration shown in FIG. 1, the bit width of the input/output data is 1 bit or 4 bits depending on the control signal from the mode control circuit 60.
A configuration is shown in which the bits are selectively switched. In response to the 2-bit internal column address signal from the column address latch 40, the selector 62 selects 1 bit of the 4 bits of data read out simultaneously when the input/output data pit width is 1 bit. The signal is applied to the buffer 63. Similarly, when the input/output data pit width is 4 bits, the selector 62 transmits the 4-bit data read simultaneously to the I10 buffer 63 as is. This first
In the configuration shown in the figure, memory cell array block M
1 to M16 are further divided into four sub-blocks, and a 1-bit memory cell is selected from each sub-block in response to a 14-bit internal column address signal.

Furthermore, in order to define the internal operation timing and data input/output write/read operations of this DRAM, the input terminal 11
Row address strobe signal RAS applied via
RA generates internal control signals necessary for row selection in response to
In response to the S-system clock generator 12, the column address strobe signal CAS applied via the input terminal 13, and the internal control signal from the RAS-system clock generator 12, CAS system clock generator 14 that generates internal control signals, and CAS system clock generator 5i14.
R/W clock generator 1 that generates a signal that provides data input/output operation timing in response to an internal control signal from
R/W1.5, and R/W1. An II controller 16 is provided.

FIG. 6 shows the memory cell array block Ma shown in FIG.
FIG. 3 is a diagram schematically showing the configuration of a main part of Mb, and is a diagram showing a mode of activation of word lines in each memory cell array block M1 to M16.

Each of the repeaters R1 to R14 receives a drive signal φ1(i-1
~15), and transmits the selected word line potential in the previous stage memory cell array block Mil:3 onto the selected word line in the subsequent stage memory cell array block Mi+1.

Row decoders 50a and 50b each receive activation signal φ0.
．． It is activated in response to φ8, decodes applied 8-bit internal row address signals RAO-RA7, and selects the corresponding word line. These drive signals φO to φ15 are generated by delaying the externally applied row address strobe signal RAS by a predetermined time. Therefore, in each of memory cell array blocks M1 to M16,
The rising timings of the selected word line potentials are all different, and the selected word line potentials are sequentially transmitted from memory cell array block M1 to block M16.

Sense amplifiers included in each of blocks 81-B16 are activated in response to sense amplifier activation signals φSO-φS15. Sense amplifier activation signal φsO to φs15
are activated after the potential of the word line of each corresponding block rises.

That is, each of the sense amplifier activation signals φSO to φS15 is generated by delaying each of the drive signals φ0 to φ15 by a predetermined time. Therefore, the activation timing of the sense amplifiers in each memory cell array block M1 to M16 is different. As a result, when a word line in one row is selected, the activation timing of the sense amplifiers for detecting and amplifying the 64-bit memory cell data is different, so the peak current that flows when the sense amplifiers are activated is can be dispersed, and fluctuations in the substrate 7d can be reduced.

After the selected word line potential in each memory cell array block M1 to M16 rises by the outputs of row decoders 50a and 50b, internal column address signals CAO to CAl
0, the column decoder included in blocks 81 to B16 connects one bit of the memory cell of the 64-bit data field to the I10 bus (if the output data is 1 bit wide).

FIG. 7 shows an example of a specific configuration of the repeater.

As described above, each memory cell array block has the same number of rows. Repeater Rn (n-1 to 14) includes a NAND gate 90 provided between each of the word lines of the previous memory cell array block and each of the subsequent memory cell array blocks, and an inverter 91 that receives the NAND gate output. include. NAND gate 90 receives the word line potential of the corresponding preceding memory cell array block at one input, and receives the drive signal φn at the other input. The inverter 91 receives the NAND gate 90 output,
It is transmitted to the subsequent memory cell array block. That is, for word line WLI, NAND gate 90-1
and an inverter 91-1 are provided. Word line WL2
for NAND gate 90-2 and inverter 9
1-2 is provided. NAN for word line WL3
A D gate 90-3 and an inverter 91-3 are provided. The bit lines that define the columns in each memory cell array block (the figure shows a folded bit line configuration and one column is defined by the bit lines BL and BL) detect the signal potential on the corresponding column. A sense amplifier SA for amplification is provided.

Therefore, since 64 columns are connected to the word line of one row, the sense amplifier SA also has a 16M bit DRA.
In the configuration of M, 64 pieces are provided. Sense amplifier SA is activated in response to sense amplifier activation signal φsn generated at different timings within each block.

In the above configuration, the signal potential on the selected word line (assuming word line WLI is selected in FIG. 7) rises in memory cell array block Mn, and then sense amplifier SA is activated in response to sense amplifier activation signal φsn. When the word line is selected, the data held by the memory cell connected to the selected word line is determined on the bit line. Next, when the drive signal φn+1 rises to the "H" level, only the signal potential of the selected word line is at the mHs level, so only the output of the NAND gate 90-1 connected to the selected word line WL1 is at the "L0" level. becomes. Therefore, memory cell array block Mn+1 corresponding to this selected word line WLI
Only the signal potential on the word line rises to "Ho". This operation is repeated in each memory cell array block. In this configuration, activation of the sense amplifier SA occurs when the word line potential in each memory cell array block is determined. The memory cell array block Mn and the memory cell array block Mn
+1, the activation timing of the sense amplifier SA is different. This makes it possible to disperse the peak current that flows when the sense amplifier SA is activated, as described above, reducing current consumption and preventing malfunctions due to fluctuations in substrate current, etc.

FIG. 8 shows a 16M which is an embodiment of the present invention shown in FIG.
A signal waveform diagram showing operation timing during access operation of a bit DRAM is shown. Referring to FIG. 8, the operation of a 16 Mbit DRAM, which is an embodiment of the present invention, will be briefly described. When the row address strobe signal RAS applied from the outside through the input terminal 11 falls to the "L" level, this semiconductor memory device is activated, and in response, the row address latch 30 is activated at the address input terminal 20.
It latches the 8-bit row address given to it, generates 8-bit internal row addresses RAO-RA7, and supplies them to row decoders 50a and 50b. Row decoder 50a is activated in response to drive signal φ0 from RAS clock generator 12, and receives applied internal row address signal RAO~
RA7 is decoded and the potential of the selected word line in memory cell array block M1 is raised to "H" level.

The potential on the selected word line in memory cell array block M1 rises, and the signal potential (read potential) in each column
After this is established, sense amplifier SA in memory cell array block Mnl is activated in response to sense amplifier activation signal φsO, and senses, amplifies, and latches the signal potential on that column.

Subsequently, due to the function of repeater R1, the potential on the selected word line in memory cell array block M2 rises.
The signal potential on the column connected to the selected word line is determined in the same manner as described above. This operation is sequentially repeated for the memory cell array blocks M3 to M16, and after the activation and sensing operations of the sense amplifiers in each memory cell array block M1 to M16 are completed, the column address strobe signal CAS applied to the input terminal 13 is " L″″″
The level goes down. In response, column address latch 40 takes in the 16-bit address signal applied to address input terminal 20 and provides 16-bit internal column address signals CAO-CA15 to the column decoder included in clocks B1-B16. The column decoder decodes the applied 16-bit column address signal, selects one of the 64 bits connected to the selected word line, and connects it to the I10 bus (however, in this configuration, (input/output data is 1 bit).

Next, after the access to this memory cell is completed, the signal RA
By raising the signal CAS to "H" - palindrome and then lowering it to "L" level again while S is held at "L" level, the 16-bit address signal applied to the address input terminal 20 becomes columnar. taken into the address latch 40,
An internal column address signal is generated and provided to the column decoder.

In response, one bit of the 64-bit data field is again selected and connected to the I10 bus.

The data size of one page is 64 bits, and this 6
All four bits can be accessed at high speed by simply toggling the signal CAS and externally applying the column address accordingly. Therefore, in this access operation, the 64-bit memory cell can be accessed simply by the signal CAS and the column address instead of using both the signal RAS and the signals C and AS. This 16 Mbit DRAM can be operated in the same manner as 64
It can be used as a bit pseudo SRAM.

FIG. 9 shows an example of a circuit configuration for generating a sense amplifier activation signal and a drive signal for driving a repeater.

Referring to FIG. 9, a circuit that generates signals for driving repeaters and sense amplifiers includes a RAS buffer 100 that receives an externally applied row address strobe signal RAS and generates an internal control signal RAS; Delay circuits D1 to D8 are provided that delay internal control signals RAS from the buffer by a predetermined time and output the delayed signals.

Each of delay circuits D1-D8 are connected in cascade. As is clear from the configuration of FIG. 9, sense amplifier activation signal φs
i is the signal φ that drives the repeater corresponding to that block
“After a predetermined period of time has elapsed after i rose to H level”
The H'' level rises. As shown in the operation waveform diagram of FIG. 10, with this configuration, the repeater is driven in each block, and after the selected word line potential in that block rises, the sense amplifier included in that block is driven. This sense amplifier activation and word line selection operation can be sequentially transmitted to the subsequent memory cell array block in each memory cell array block.

FIG. 11 and FIG. 12 show one embodiment of the present invention.
The operational waveform diagrams of the 6M bit DRAM in normal mode and page mode are shown in more detail. As shown in the operational waveform diagram during normal mode data read operation in FIG. 11, each of the delay circuits D1 to D8 shown in FIG. 9 has a delay time of approximately 50 ns, and When the strobe signal qRAs falls to the 'L' level, the row address from the outside is taken into the device and an internal row address is generated, and the word line and sense amplifier in each memory cell array block M1 to M16 are activated. It takes about 850ns to 900ns to complete.After that, the column address strobe signal CAS becomes "L".
The 16-bit column address applied to the address input terminal 20 is taken in, and internal column address signals CAO to CA15 are generated. 1-bit memory cell data is output.The write/read operation of this data is instructed by the R/W control circuit 16 shown in FIG. It is carried out under the control of

In the page mode of the high-speed serial access mode, as shown in the detailed operational waveform diagram during reading in Figure 12, the operation is the same as in the normal mode shown in Figure 11 until the first 1 bit of data is read. However, the second access is performed by toggling the column address strobe signal CAS to take in a column address from the outside.

Therefore, it is not necessary to read the row address and column address bit by bit as in the normal mode, and data can be read out at high speed.

In the above configuration, word lines and sense amplifiers are activated sequentially from memory cell array block M to memory cell array block M16. However, instead of this configuration, the memory cell array blocks Ma and Mb may be configured to be accessed simultaneously and in parallel. That is, one memory cell array block in memory cell array block Ma and one memory cell array block in memory cell array block Mb may be configured to be accessed simultaneously. In this case, compared to a configuration in which memory cell array blocks are activated one by one, the time required to activate all memory cell array blocks is about half, and faster access is possible.

Furthermore, instead of the above configuration, the order of activating the memory cell array blocks may be reversed from block M16 to block M1.

That is, the activation timing of the sense amplifier and selected word line is different in each memory cell array block, and if the configuration reduces the peak current flowing when the sense amplifier is activated, the same effect as the above embodiment can be obtained. can.

Furthermore, the 16 Mbit DR according to the present invention as described above
In AM, the number of word lines is 256, and all word lines can be selected with an 8-bit row address. Therefore, in order to refresh all 16 Mbit memory cells, in conventional DRAM, 2
'2 (256 x 16) times of refresh cycles can be reduced to 256 times, reducing the time required for refresh, improving memory access efficiency and ease of timing design of a system using this DRAM. can improve sex.

Furthermore, in the 16 Mbit DRAM according to the present invention, the data size of one page is 64 bits, and it is possible to perform so-called hidden refresh in which refresh operation is performed internally in parallel with external memory access. DRAM to 64 bit PS
It becomes possible to use it as RAM.

Next, a configuration for easily performing this hidden fresh will be described with reference to FIG. 13.

FIG. 13 is a diagram showing a main part of a configuration for easily performing a refresh operation of an ancient iDRAM according to the present invention. FIG. 13 shows the configuration of two pairs of bit lines, that is, two columns, two rows of word lines, their associated sense amplifiers, and main functional sections. Referring to FIG. 13, a latch circuit constructed using, for example, an SRAM cell is provided for latching data on each column, that is, bits MBL and BL. Latch circuit and bit line BL,
A transfer gate transistor Q is provided between BL and turned on or off in response to a transfer signal φ[n. Latch circuit and data input/output bus I10. A data input/output bus I10.I10 selectively connects a latch circuit in response to the output from the column decoder 6. I10 gates TR, TR' for transmitting to I10 are provided.

FIG. 14 is a signal waveform diagram showing the operation timing of activating the transfer gate and sense amplifier shown in FIG. 13. As shown in FIG. 14, the transfer control signal φTn is the sense amplifier activation signal φ in the corresponding memory cell array block.
After sn rises to the "H" level and the sense amplifier is activated, it rises to the "H" level.As a result, the signal sensed and amplified by the sense amplifier is transferred to the latch circuit via the transfer gate Q that is in the on state. This transfer control signal φ
Tn is the last memory cell array block, for example, M
Sense amplifier activation signal φs15 in 16 is “H”
After rising to the level and completing the transfer operation in the memory cell array block, it falls to the "L" level, electrically disconnecting the latch circuit and the sense amplifier.

FIG. 15 shows an example of a circuit configuration for generating the signal shown in FIG. 14. Referring to FIG. 15, the transfer control signal generation circuit activates a delay circuit 150 that receives a sense amplifier activation signal φsn, delays it by a predetermined time, and outputs it, and a sense amplifier of the memory cell array block that is activated last. A delay circuit 151 receives the sense amplifier activation signal φs15 to output the signal after a predetermined time delay;
The SR flip-flop 152 receives an output from the reset human power R. Transfer control signal φTn is applied from the Q output of SR flip-flop 152. Next, the first
The data transfer operation will be explained in detail with reference to FIGS. 3 to 15.

When the row address strobe signal RAS falls to the "L" level and a predetermined time has elapsed, the sense amplifier activation signal φS for activating the sense amplifiers in this memory cell array block rises to the H level. In response, the sense amplifier SA is activated to detect and differentially amplify the signal potential on the bit line.The signal potential on the bit line pair is sensed and amplified by the sense amplifier SA,
Once the signal potential is determined, the flip-flop 15
Transfer control signal φTn from 2 rises to "H" level.

This turns on the transfer gate transistor Q, and the data latched by the sense amplifier SA is transferred to the latch circuit. The latch circuit latches this transferred data. The transfer control signal φTn goes to the "L" level when the sensing operation in the last memory cell array block M15 is completed, that is, after a predetermined period of time has passed after the sense amplifier activation signal φs15 in the memory cell array block M15 rises to the "H" level. When the signal falls, the sense amplifier SA and the latch circuit are disconnected.

This results in 64 data fields corresponding to one page of data fields.
The bit data is 64Kfl! It is latched by the latch circuit of I. This latch circuit selection is performed by selecting the latch circuits connected to the corresponding column by the column decode signal from the column decoder 6.
10 gates) to the data input/output bus I10. Therefore, sense amplifier S
After data is transferred from A to the latch circuit, the column selection operation for each memory cell array block can be performed independently of the row selection operation. Therefore, after data is latched in the latch circuit, each memory cell array block can be refreshed.

In particular, if an automatic refresh function or a self-refresh function is provided, it becomes possible to perform memory cell access using a column address in parallel with the refresh operation, so that a 64-bit pseudo-static RAM can be realized.

That is, as shown in FIG. 16, the signal RAS is set to 'L'.
After lowering the level and latching one page of data in each memory cell array block into the latch circuit,
By raising the signal RAS to the "H" level again and lowering the signal CAS to the "L" level in this "H" level state, in this 16 Mbit DRAM, the CAS before R
While S refresh is performed, the latch circuit L can be accessed in parallel at the same time, and one column can be selected in accordance with an external column address to read memory cell data. In the CAS before RAS refresh cycle, the time required for all word lines in one row to be activated is about 750 ns to 800 S, and one row of memory cells is refreshed during this period.

Furthermore, instead of this CAS-before-RAS configuration, if there is a self-refresh function that automatically generates a refresh address during a refresh instruction in response to an external refresh instruction signal, there is no need to toggle the signal RAS. Refreshing can be performed more easily. This self-refresh instruction can be performed using an 8-bit row address, for example, through eight address input bins that are unnecessary when applying a row address.

In this case, the 8-bit control signal is sent to the control signal latch circuit 7.
0, and is latched in response to the row address strobe signal RAS. When the control signal latched by the control signal latch circuit 70 specifies the refresh mode, an internal refresh instruction signal REF is generated under the control of the mode control circuit 60, and the refresh count is set to 6.
Give to 1. Refresh counter 61 receives internal refresh instruction signal R from mode control circuit 60.
It is activated in response to EF and generates a refresh address. Row address latch 30 selectively passes the refresh address from refresh counter 61 in response to an internal refresh instruction signal from mode control circuit 60 and supplies it to row decoders 50a, 50b as internal row addresses RAO-RA7. This results in
In response to selection signals from row decoders 50a and 50b, a refresh operation can be performed in each memory cell array block Ma and Mb in parallel with a column selection operation for the latch circuit.

Furthermore, in addition to the above configuration, it is also possible to detect and correct errors in memory cell data read during refresh. This configuration is shown as ECCCC circuits-1 to E16 in FIG. Next, a configuration for detecting and correcting errors in memory cell data during this refresh operation will be briefly described. FIGS. 17A and 17B are diagrams showing an error detection and correction method used in a QDRAM according to the present invention.

In the configuration shown in FIGS. 17A and 17B, 9-bit memory cells are used as information bits, 7-bit memory cells are used as check bits, and a total of 16-bit memory cells are connected to one word line WL. An example of the configuration when connected is shown. This configuration is described, for example, in Nikkei Microdevice March 1987 issue, pages 69 to 71. Nine information bits are stored in memory cells MC0-MC8. Memory cell M
C9 to MC15 are used as check bits for storing 7 parity check bits.

In this configuration, the 16-bit memory cells are logically arranged in two-dimensional horizontal and vertical groups. At this time, as shown in FIG. 17B, the memory cells are arranged in numerical order so that the memory cells are sequentially arranged diagonally in a matrix of 4 rows and 4 columns. That is, in the memory cell arrangement shown in FIG. 17A, four physically adjacent memory cells are used as a unit, and the memory cells within this unit are grouped so that they belong to different horizontal and vertical groups. With such grouping,
Both the horizontal group and the vertical group can have a divided selector configuration that selects one memory cell from adjacent 4-bit memory cells. The horizontal group and vertical group are selected by vertical group selection signals VO to v3 and horizontal group selection signals HO to H3. Further, each of memory cells MC9 to MC15 stores a parity bit in a horizontal group or a parity bit of a memory cell in a vertical group. This E
An example of a specific configuration of the CC circuit is shown in FIG. 18th
Also in the configuration shown in the figure, a configuration is shown as an example in which a total of 16 bits of memory cells, including 9 bits of information bits and 7 bits of check bits, are connected to one word line WL.

In FIG. 18, memory cells are divided into groups of four memory cells to form four memory cell groups. Horizontal selections 3H31 to H94 are provided to select one row in the horizontal direction for each of these four memory cell groups. Horizontal direction selector f(S
Each of cells 1-H54 selects one of the 4-bit memory cells in response to the horizontal group selection signal HO-H3.

Vertical selectors VSI to vS4 are provided for each memory cell group to select one vertical row among the four memory cell groups. Each of the vertical selectors VSI to VS4 receives a vertical group selection signal
0 to V3 to select one memory cell within the corresponding group.

The vertical group selection signals applied to each of the vertical selectors VS1 to VS4 are shifted one bit at a time. Horizontal group selection signals HO to H3 for selectors that select groups in the horizontal direction are sent to each selector H in the same order.
3I-H84.

In order to perform a horizontal parity check, ExOR gates HEI-HE4 are provided for receiving the outputs of the respective horizontal selectors H8I-H34 and performing addition in module 2. To perform a vertical parity check, ExOR gates VEI-VE4 are provided for performing modulo-2 addition of the outputs of the vertical selectors VSI-VS4.

Multiplexer MUX receives horizontal group selection signals HO~H
3 and vertical group selection signals VO to V3, the data for this memory cell is given to the ExOR gate 200, and the output of this ExOR gate 200 is written again to the selected memory cell. .

ExOR gate HE is used to perform error detection of memory cells selected by horizontal and vertical group selection signals.
4. An AND gate 201 is provided that receives the VE4 output. Next, the operation will be briefly explained.

During error detection and correction, a column address signal (horizontal/vertical selection signal; in the configuration shown in FIG. 1, this is sequentially generated from the refresh count 61 by a control signal from the mode control circuit 60) is sent to each selector. H.S.
I~H54 and VSI~VS4. This selector selects memory cells in each row in the horizontal direction and vertical group direction, and the memory cell data in each row is sent to the ExOR circuits HEI to HE4°VEI.
~Given to VE4. If one memory cell data in the horizontal selection group is incorrect, Ex
The OR gate HE4 output becomes all, and if all are correct, it becomes "0°. Therefore, if the data of the selected memory cell located at the intersection of the horizontal group and the vertical group is incorrect, the output of the ExOR gate HE4.
Both VE4 outputs become 1", and the ANp gate 201 output also becomes "1"("H") level. Multiplexer M
The UX reads the 1-bit memory cell data specified by the horizontal and vertical group selection signals and performs ExOR.
It is given to gate 200.

The ExOR gate 200 has an AND gate 201 output of "
In the case of H# level, the multiplexer MUX output is inverted and output. On the other hand, the AND gate 201 output is “L”
In the case of level, the output data from the multiplexer MUX is passed through as is. Multiplexer M U X transfers the output data from ExOR gate 200 back to the selected memory cell and writes it there. This allows error detection and correction of memory cell data.

Using the above configuration, if the refresh address counter periodically generates the horizontal group selection signals HO to H3 and the vertical group selection signals VO to V4 in sequence, it is possible to detect errors in memory cell data connected to the selected row. and corrections may be made. In this case, since the memory cells connected to one row of word lines are 64 bits, each memory cell block also has 4 bits.

Therefore, in order to perform error detection and correction by sequentially reading memory cell data of 4 bits each, it is necessary to perform error detection and correction 4 times, and one refresh cycle can detect and correct errors in all memory cell data. It may become impossible to make corrections. Therefore, in this case, in the configuration shown in FIG. 17, each column is further divided into subblocks of an appropriate block size within one memory cell array block, and error detection and correction is performed individually on the divided subblocks. If this is done, error detection and correction of all 64 bits of memory cell data can be carried out reliably with a margin in one refresh cycle.

By providing the above configuration, error detection and correction of memory cell data can be performed during refresh operation, and there is no need to perform error detection and correction when reading data, allowing memory cell data to be read at higher speed. can.

Furthermore, in the large JiDRAM, the bit width of the input/output data is normally set by a master slicing method or by switching the connection of bonding pads. In this case, the bit width of input/output data is fixed and cannot be changed. However, as shown in FIG.
By applying a data bit length designation signal using the bit address input terminal and operating the selector 62 and I10 buffer 63 with this control signal, the bit length of input/output data can be set as appropriate depending on the use of the DRAM. It becomes possible to do so. In the configuration shown in FIG. 1, 4-bit memory cells are simultaneously selected by 2-bit internal column address signals CAO and CAL, and 1 bit or 4 bits of the 4-bit memory cell data are sent to I10 via selector 62. A configuration connected to buffer 63 is shown.

However, if instead of this configuration, a 3-bit column address signal is applied to the selector 62, the number of bits of input/output data can be set to 8 bits. Further, with this configuration, the bit length of input/output data can be freely set to 1 bit, 4 bits, or 8 bits depending on the purpose.

Furthermore, although the specific configuration is not shown, the number of address input terminals that are not used when applying a row address is 8 bits, so 28 types of operation modes can be specified by this 8-bit signal, and various It is possible to provide configurations that control a variety of internal operations. As an example of such a configuration, a bit mask function, a bit comparison function, etc. can be considered.

In the above embodiment, a 16 Mbit DRAM is used as an example of the large iDRAM, but the storage capacity of the large iDRAM is not limited to this, and the same effects as in the above embodiment can be obtained even if other storage capacities are used. Obtainable.

Furthermore, in the above embodiment, the configuration in which the row address and column address are applied in a time-division multiplexed manner has been described, but instead of this, the row address and the column address are applied simultaneously, and the RAM ( For example, PSDRAM
), the data size of one page can be expanded by making the number of bits of the row address and column address different, and the same effect as the above embodiment can be obtained.

[Effects of the Invention] As described above, according to the present invention, the number of bits constituting a row address is smaller than the bits constituting a column address, so the data size of one page can be expanded and the speed can be increased. access can be realized.

Furthermore, by reducing the number of row address bits, the number of word lines is reduced, so all memory cells can be refreshed in fewer refresh cycles, simplifying the refresh configuration and improving memory access efficiency. becomes.

Furthermore, with the above configuration, the capacity of one page is, for example, 1
In the case of 6M bit DRAM, there are 64 bits, so
Since these 64 bits can be accessed using only the column address, the large ffiDRAM can be used as a pseudo-static RAM.

Furthermore, a data latch circuit is provided between the sense amplifier provided for each column and the data output bus, and after the sense amplifier is activated, the sense amplifier and the latch circuit are separated from each other. Since the circuit is configured so that it can be accessed using a column address, it is possible to refresh the memory cell in parallel with access to the memory cell using the column address, without having to consider the refresh operation. This makes it possible to improve the access efficiency of the DRAM, and to facilitate the timing design of a memory system using the DRAM.

Furthermore, since the activation timing of the selected word line and sense amplifier is different in each memory cell array block, the peak current that occurs when the sense amplifier is activated can be dispersed, reducing current consumption and lowering the substrate potential. Malfunctions due to fluctuations can be prevented.

Furthermore, since the page data size has been expanded, when this large-capacity DRAM is used as a video memory that writes and reads image data at high speed, it is possible to write and read image data at high speed, and in real time. It is possible to obtain a video memory that can be used in a system for processing image data.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of the overall configuration of a large-capacity dynamic semiconductor memory device, which is an embodiment of the present invention. FIG. 2 is a diagram showing the arrangement of external bin terminals for inputting and outputting signals of a conventional IM bit DRAM. FIG. 3 is a diagram showing the overall general configuration of a conventional IM bit DRAM. FIG. 4 is a diagram showing the configuration of a main part of a conventional DRAM memory cell array, in which a pair of bit lines and related circuit parts are schematically shown. Figure 5 shows the conventional 1
1 is a diagram showing a schematic configuration of a 6M bit DRAM, and a diagram schematically showing a divided memory cell array block configuration thereof. FIG. FIG. 5 is a diagram schematically showing the structure of a memory cell array section of a large-capacity dynamic semiconductor memory device according to an embodiment of the present invention. FIG. 7 is a diagram schematically showing the structure of a repeater connecting adjacent memory cell array blocks of a large-capacity dynamic semiconductor memory device according to an embodiment of the present invention. FIG. 8 is a signal waveform diagram schematically showing the operation of a large-capacity dynamic semiconductor memory device according to an embodiment of the present invention. FIG. 9 is a diagram showing an example of a circuit configuration for generating a signal for controlling the repeater shown in FIG. 7. FIG. 10 is an operation waveform diagram showing the timing of generation of the sense amplifier activation signal and repeater activation signal shown in FIG. 6. FIG. 11 is a signal waveform diagram showing the operation of a large-capacity dynamic semiconductor memory device according to an embodiment of the present invention when reading data in a normal mode. 1st
FIG. 2 is a signal waveform diagram showing the operation timing when reading data in the page mode of a large-capacity dynamic semiconductor memory device according to an embodiment of the present invention. FIG. 13 is a diagram showing the configuration of main parts of a large-capacity dynamic semiconductor memory device according to another embodiment of the present invention, in which a data latch is used to perform memory cell access and refresh operation in parallel. FIG. FIG. 14 is an operational waveform diagram showing the timing relationship between the transfer control signal that drives the transfer gate shown in FIG. 13 and the sense amplifier drive signal. FIG. 15 is a diagram showing an example of a circuit configuration for generating the transfer control signal shown in FIG. 13. FIG. 16 is a signal waveform diagram showing the operation in a dynamic semiconductor memory device according to another embodiment of the present invention, and is a signal waveform diagram showing the operation when external access and internal refresh are performed simultaneously in parallel. . 17A and 17B are diagrams showing the principle of the operation method of an error detection/correction circuit used in a large-capacity dynamic semiconductor memory device which is another embodiment of the present invention, and FIG. 17A shows one FIG. 17B is a diagram showing an arrangement in which one row of memory cells is logically arranged in two dimensions. FIG. 18 is a diagram showing an example of a specific configuration of an error detection/correction circuit used in a large-capacity dynamic semiconductor memory device according to the present invention. In the figure, Ma and Mb are memory cell array blocks,
M1 to M16 are further divided memory cell array blocks, and B1 to B16 are sense amplifiers provided corresponding to each memory cell array block. Block E1 including column decoder, I10 gate, etc.
~E16 is an error detection/correction circuit block that operates during refresh operation, R1-R14 is a repeater for sequentially transmitting word line signal potentials, 11 is a row address strobe signal input terminal, 12 is an RAs system clock generator, 1
3 is a column address strobe signal input terminal, 14 is C
AS system clock generator, 15 is an R/W clock generator,
16 is an R/W controller, 20 is an address input terminal, 3° is a row address latch, 40 is a column address latch, 6
0 is a mode control circuit, 70 is a control signal latch circuit, 62 is a selector, and 63 is! 10 buffers, 90-1
~90-3 is a NAND gate that constitutes a repeater, 91
-1 to 91-3 are inverters forming the repeater, SA
is a sense amplifier, L is a latch circuit consisting of an SRAM cell, and TR. TR' is an I10 gate, Q is a transistor forming a transfer gate provided between the sense amplifier and the latch circuit, 50a and 50b are row decoders, and 6 is a column decoder. In each figure, the same reference numerals indicate the same or corresponding parts. Patent Applicant Richard Charles Foss No. 2 Wi Figure 3 Figure 9! ! ! DI, DB: Masamichi section Figure 10 Figure 14 Figure 18

Claims (10)

[Claims] (1) A plurality of memory cells arranged in a matrix of rows and columns, a plurality of word lines each selecting one row of the plurality of memory cells, and each word line selecting one column of the plurality of memory cells. A dynamic semiconductor memory device including a plurality of memory cell array blocks each having a plurality of bit lines to be selected, wherein one word line is selected from each of the plurality of array blocks in response to an externally applied row address. and means for selecting at least one column as a whole from the plurality of memory cell array blocks in response to an externally applied column address, the number of bits forming the column address forming the row address. A large-capacity dynamic semiconductor memory device with a larger capacity than the number of bits. (2) Claim 1 further comprising means for activating word lines selected from each of the plurality of memory cell array blocks at different timings for each block in response to the row selection means output signal. A large-capacity dynamic semiconductor memory device as described in 2. (3) The word line activation means is provided between adjacent blocks of the plurality of memory cell array blocks, and selects the subsequent block after delaying the selected word line potential in the previous block by a predetermined time. 3. A large-capacity dynamic semiconductor memory device according to claim 2, further comprising means for transmitting data to a word line. (4) Each of the plurality of memory cell array blocks includes the same number of rows, and the word line potential transmission means transmits a different potential to each of the plurality of memory cell array blocks in response to an externally applied row address strobe timing signal. A block activating means for applying an activation signal at a timing, and a word line defining a row of the same number between adjacent memory cell array blocks, and responsive to an activation signal from the block activating means, 4. The large-capacity dynamic semiconductor memory device according to claim 3, further comprising means for transmitting the potential of a word line in a corresponding preceding block to a corresponding subsequent word line. (5) Each of the plurality of columns in each of the memory cell array blocks is provided with sense amplifier means for detecting and amplifying the signal potential on the corresponding column, and the sense amplifier means is activated for each block. 5. The large-capacity dynamic semiconductor memory device according to claim 4, further comprising means for activating said sense amplifier means in response to word line activation in a corresponding block so as to have different timings. (6) a data bus for connecting the column selected by the column selection means of the plurality of memory cell array blocks to a data input/output section; and between each of the columns in each of the memory cell array blocks and the data bus. a means for latching data transmitted to a corresponding column; and a means for latching data transmitted to a corresponding column; and a means for detecting and amplifying the sense amplifier means in the corresponding memory cell array block, provided between the latch means and each corresponding column. means for responsively electrically isolating said latching means from a corresponding column; and means provided between each of said latching means and said data bus in response to said column selecting means output signal; 5. The large-capacity dynamic semiconductor memory device according to claim 4, further comprising means for electrically connecting latch means coupled to said data bus. (7) refresh instruction signal generation means; means provided in each of the memory cell array blocks for storing error detection data formed in relation to data stored in the memory cell array in the block; and the refresh means for generating an internal row address in response to an instruction signal and applying it to the row selection means; and a means for generating an internal row address and applying it to the row selection means; The memory cell data connected to the selected word line and the error detection data related to this memory cell data are read, and the error detection and correction of the read memory cell data is performed on the read error detection data. 2. The large-capacity dynamic semiconductor memory device according to claim 1, further comprising means for performing the data based on the data. (8) Selecting a memory array consisting of a plurality of memory cells arranged in a matrix of rows and columns, a plurality of word lines for selecting one row of the memory array, and one column of the memory cell array. A large-capacity dynamic semiconductor memory device having a plurality of bit lines for external address input terminals and a plurality of external address input terminals, the device comprising: means for receiving a row address applied from the outside and generating an internal row address signal; means for receiving an operation mode designation signal applied from the outside via the remaining external address input terminals at the same timing as the row address; means for receiving a column address applied from the outside through the plurality of external address input terminals in a time division multiplexed manner with the operation mode designation signal, and generating an internal column address, the number of bits constituting the external row address being A large-capacity dynamic semiconductor memory device in which the number of bits constituting the external column address is smaller than the number of bits constituting the external column address. (9) a data input/output unit; means for selecting a plurality of memory cells from the memory array in response to the external row address and the external column address; and means for selecting the plurality of memory cells in response to the operation mode designation signal. Claim 8 further comprising means for connecting one or more of the memory cells to the data input/output section.
A large-capacity dynamic semiconductor memory device as described in 2. (10) A large-capacity dynamic semiconductor memory device in which a row address and a column address are externally applied via an external address terminal in a time division multiplexed manner, wherein the number of bits making up the row address makes up the column address. A large-capacity dynamic semiconductor memory device characterized in that the number of bits is smaller than the number of bits.