JPH01299064A - Thermal recorder - Google Patents

Thermal recorder

Info

Publication number
JPH01299064A
JPH01299064A JP63129820A JP12982088A JPH01299064A JP H01299064 A JPH01299064 A JP H01299064A JP 63129820 A JP63129820 A JP 63129820A JP 12982088 A JP12982088 A JP 12982088A JP H01299064 A JPH01299064 A JP H01299064A
Authority
JP
Japan
Prior art keywords
signal
picture
control circuit
shift register
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63129820A
Other languages
Japanese (ja)
Inventor
Sadamiki Kato
加藤 貞幹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63129820A priority Critical patent/JPH01299064A/en
Publication of JPH01299064A publication Critical patent/JPH01299064A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To constitute each circuit in the number of the half of conventional devices, and to obtain a low-cost device by mounting a power supply control circuit selectively supplying electric power at every heating resistor corresponding to a divided picture signal and a reading control circuit generating a transfer clock, a data latch signal and a printing command signal. CONSTITUTION:When the number of the reading of the same picture signal is twice and the number of the picture elements of one scanning line four, a reading control circuit 1 reads a picture signal corresponding to one scanning line stored in a line memory 2 as the first time, and inputs the picture signal to the S1 of a shift register 4 as an input picture signal (a) while supplying the S1 with a transfer clock (b) at every two picture-element period conformed to the picture element timing of odd-number picture elements. The reading control circuit 1 reads a picture element signal as the second time, and inputs the picture element signal to the S1 of the shift register 4 as an input picture element signal (a) while supplying the S1 with a transfer clock (b) at every two picture-element period conformed to the picture element timing of even-number picture elements. On the other hand, a power supply control circuit 3 supplies the R1 and R3 of a heating resistor 8 in the odd number with a power supply f1 after the completion of the transfer of the first picture signal and the R2 and R4 of the heating resistor 8 in the even number with a power supply f2 for the second time.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はファクシミリなどに使用される感熱記録装置に
関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a thermal recording device used in facsimiles and the like.

〔従来の技術〕[Conventional technology]

ファクシミリなどに使用される感熱記録装置においては
、現在、記録する一走査線内の画素数に相当する段数の
シフトレジスタを有し、シフトレジスタの各段に接続さ
れた同じく走査線内の画素数に相当するドライバ回路に
よって、記録する画素位置の発熱抵抗体を通電する構成
が一般的である。第3図は、従来の感熱記録装置の一例
のブロック図、第2図は従来例の動作を説明するための
タイミング図である。説明を簡単にするため一走査線内
の画素数を4と仮定して示しである。
Thermal recording devices used in facsimiles and the like currently have shift registers with the number of stages corresponding to the number of pixels in one scanning line to be recorded, and each stage of the shift register is connected to the number of pixels in the same scanning line. A typical configuration is such that a driver circuit corresponding to the above energizes a heating resistor at a pixel position to be recorded. FIG. 3 is a block diagram of an example of a conventional thermal recording device, and FIG. 2 is a timing diagram for explaining the operation of the conventional example. In order to simplify the explanation, it is assumed that the number of pixels in one scanning line is four.

入力画信号aはシフトレジスタS1〜S4の左端S1に
入力され、転送クロックbにより順次S1、S2、S3
、S4と右側へ転送される。転送が終了すると各シフト
レジスタ81〜S4に転送されたー走査線分の画情報2
1〜p4はデータラッチ信号Cによりデータラッチし1
〜L4にラッチされる。この時点でシフトレジスタ81
〜S4は次の一走査線分の画信号入力が可能となる。
The input image signal a is input to the left end S1 of the shift registers S1 to S4, and is sequentially transferred to S1, S2, S3 by the transfer clock b.
, S4 and is transferred to the right side. When the transfer is completed, the image information 2 of the scanning line is transferred to each shift register 81 to S4.
1 to p4 are data latched by data latch signal C.
~Latched at L4. At this point, the shift register 81
~S4 enables image signal input for the next one scanning line.

データラッチL1〜L4のデータ出力d1〜d4は、論
理積回路A1〜A4により印字命令信号eとの間の論理
積をとられ、印字命令信号eが真で且つデータ出力d1
〜d4が黒情報であるときのみ電源fにより給電された
発熱抵抗体R1〜R4をドライバ回路D1〜D4により
通電する。ここでは説明の簡単のため一走査線内の画素
数を4として説明したが、実際には例えば210mm幅
の用紙に8画素/ m mの画素密度で記録する感熱記
録装置においては一走査線内の画素数は1680にも及
ぶ、従って第3図で説明したようなシフトレジスタ・デ
ータラッチ・論理積回路・ドライバ回路は例えば64画
素分ごとに一つの集積回路に実装されるのが一最的であ
る。
The data outputs d1 to d4 of the data latches L1 to L4 are ANDed with the print command signal e by the AND circuits A1 to A4, and if the print command signal e is true and the data output d1 is
Only when d4 is black information, the heating resistors R1 to R4 supplied with power by the power source f are energized by the driver circuits D1 to D4. Although the explanation here assumes that the number of pixels in one scanning line is 4 to simplify the explanation, in reality, for example, in a thermal recording device that records on 210 mm wide paper at a pixel density of 8 pixels/mm, the number of pixels in one scanning line is 4. The number of pixels is as high as 1,680, so it is best to implement the shift register, data latch, AND circuit, and driver circuit, as explained in Figure 3, on one integrated circuit for each 64 pixels, for example. It is.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の感熱記録装置においては、−走査線を構
成する画素ごとにシフトレジスタ・データラッチ・論理
積回路・ドライバなどの回路群を具備しなければならな
いため、これら回路群の素子の価格と組み込み製造価格
により装置が高価になってしまうという欠点がある。
In the above-mentioned conventional thermal recording device, each pixel constituting a scanning line must be equipped with a circuit group such as a shift register, data latch, AND circuit, driver, etc., so the cost of the elements of these circuit groups and The disadvantage is that the device becomes expensive due to the built-in manufacturing cost.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の感熱記録装置は、1走査線分の画素信号を記憶
するラインメモリと、転送クロックによって複数分の1
に分割した前記画素信号を記憶するシフトレジスタと、
このシフトレジスタの出力をデータラッチ信号によって
記憶保持するデータラッチと、このデータラッチの出力
と印字命令信号との論理積を求め出力する論理積回路と
、この論理積回路の出力に応じて発熱抵抗体に通電する
ドライバ回路と、分割した前記画信号に対応する前記発
熱抵抗体ごとに選択給電させる給電制御回路と、前記転
送クロックとデータラッチ信号と印字命令信号を発生す
る読出制御回路とを有している。
The thermal recording device of the present invention has a line memory that stores pixel signals for one scanning line, and a plurality of pixel signals based on a transfer clock.
a shift register that stores the pixel signal divided into;
A data latch that stores and holds the output of this shift register using a data latch signal, an AND circuit that calculates and outputs the AND of the output of this data latch and a print command signal, and a heating resistor that generates heat according to the output of this AND circuit. a driver circuit that supplies current to the body; a power supply control circuit that selectively supplies power to each of the heating resistors corresponding to the divided image signals; and a readout control circuit that generates the transfer clock, data latch signal, and print command signal. are doing.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。第1図
は、本発明の一実施例を示すブロック図、第2図は本実
施例の動作を説明するための制御タイミング図である0
本実施例は同一の画信号の読出口数を2回とし、−走査
線の画素数を4として説明する。
Next, the present invention will be explained with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a control timing diagram for explaining the operation of this embodiment.
This embodiment will be described assuming that the number of readout ports for the same image signal is two, and the number of pixels in the -scanning line is four.

読取制御回路1は、ラインメモリ2に蓄積されたー走査
線分の画信号をまず一回目として読み出し、入力画信号
aとしてシフトレジスタ4の81に入力すると共に、奇
数番号画素の画素タイミングに合せた2画素周期毎の転
送クロックbを供給し、入力の画素信号aを順次S1、
S2と右側へ転送させる。この時、偶数番号画素の画素
タイミングでは転送クロックbが発生しないため、画情
報p2、p4は転送されない、転送が終了すると各シフ
トレジスタ4の81、S2に転送されたー走査線分の画
情報p1、p3はデータラッチ信号Cによってデータラ
ッチ5のLl、R2にラッチされる。この時点でシフト
レジスタ4の81、S2は次の回の一走査線分の画信号
入力が可能となる。
The reading control circuit 1 first reads out the image signals for one scanning line stored in the line memory 2 and inputs them to the shift register 81 as an input image signal a, and also synchronizes them with the pixel timing of the odd-numbered pixels. A transfer clock b every two pixel cycles is supplied, and the input pixel signal a is sequentially transferred to S1,
Transfer to S2 and the right side. At this time, since the transfer clock b is not generated at the pixel timing of even-numbered pixels, the image information p2 and p4 are not transferred. When the transfer is completed, the image information for the scanning line is transferred to 81 and S2 of each shift register 4. p1 and p3 are latched into Ll and R2 of the data latch 5 by the data latch signal C. At this point, the image signals 81 and S2 of the shift register 4 can be inputted for one scanning line of the next time.

読出制御回路1から印字命令信号eが供給されるとデー
タラッチ5のLl、R2のデータ出力d1、d2は、論
理積回路6のAI、A2により印字命令信号eとの間の
論理積をとられ、印字命令信号eが真で且つデータ出力
d1、d2が黒情報であるときのみ電源で1により給電
された発熱抵抗体8のR1、R3をドライバ回路7のD
l、D2によって通電する。その結果発熱抵抗体8のR
1、R3は画情報p1、p3に応じてそれぞれ通電され
ることになる。またこのとき、発熱抵抗体8のR2、R
4は電源f2が給電されていないなめ通電されない。
When the print command signal e is supplied from the read control circuit 1, the data outputs d1 and d2 of the data latch 5 Ll and R2 are ANDed with the print command signal e by the AND circuit 6 AI and A2. , and only when the print command signal e is true and the data outputs d1 and d2 are black information, R1 and R3 of the heating resistor 8 supplied with power by the power supply 1 are connected to the D of the driver circuit 7.
1, energizes by D2. As a result, R of the heating resistor 8
1 and R3 are respectively energized according to the image information p1 and p3. Also, at this time, R2 and R of the heating resistor 8
4 is not energized because the power source f2 is not supplied with power.

次に読取制御回路1はラインメモリ2に蓄積された前回
の転送と同一の一走査線分の画素信号を二回目として読
み出し、入力画素信号aとしてシフトレジスタ4の81
に入力すると共に、偶数番号画素の画素タイミングに合
わせた2画素周期毎の転送クロックbを供給し、入力画
素信号aを順次S1、S2と右側へ転送させる。この時
、奇数番号画素の画素タイミングでは転送クロックbが
発生しないため、画情報p1、p3は転送されない、転
送が終了すると各シフトレジスタ4の81、S2に転送
されたー走査線分の画情報p2、p4はデータラッチ信
号Cによりデータラッチ5のLl、R2にラッチされる
。この時点でシフトレジスタ4の81、S2は次の一走
査線分の画信号入力が可能となる。
Next, the reading control circuit 1 reads out the pixel signal for one scanning line, which is the same as the previous transfer, stored in the line memory 2 for the second time, and uses the pixel signal 81 of the shift register 4 as the input pixel signal a.
At the same time, a transfer clock b is supplied every two pixel periods in accordance with the pixel timing of even-numbered pixels, and the input pixel signal a is sequentially transferred to the right side as S1 and S2. At this time, since the transfer clock b is not generated at the pixel timing of the odd numbered pixel, the image information p1 and p3 are not transferred. When the transfer is completed, the image information for the scanning line is transferred to 81 and S2 of each shift register 4. p2 and p4 are latched into Ll and R2 of the data latch 5 by the data latch signal C. At this point, the shift register 4 81 and S2 can receive image signals for the next scanning line.

一方、給電制御回路3は、二回目の画信号の転送終了後
偶数番目の発熱抵抗体8のR2、R4に対して電源で2
を給電し、偶数番目の発熱抵抗体8のR1、R3への電
源f1の給電を保留する。
On the other hand, the power supply control circuit 3 supplies two power supplies to R2 and R4 of the even-numbered heating resistors 8 after the second image signal transfer is completed.
, and the supply of power f1 to R1 and R3 of the even-numbered heating resistors 8 is suspended.

読出制御回路1から印字命令信号eが供給されるとデー
タラッチ5のLl、R2のデータ出力d1、d2は、論
理積回路4のAl、A2により印字命令信号eとの間の
論理積をとられ、印字命令信号eが真で且つデータ出力
d1、d2が黒情報であるときのみ電源f2により給電
された発熱抵抗体8のR2、R4は画情報p2、p4に
応じてそれぞえ通電されることになる。またこのとき、
発熱抵抗体8のR2、R4は画情報p2、p4に応じて
それぞれ通電されることになる。またこのとき、発熱抵
抗体8のR1、R3は電源f1が給電されていないため
通電されない。
When the print command signal e is supplied from the read control circuit 1, the data outputs d1 and d2 of the data latch 5 Ll and R2 are ANDed with the print command signal e by the AND circuit 4 Al and A2. Only when the print command signal e is true and the data outputs d1 and d2 are black information, R2 and R4 of the heating resistor 8 supplied with power from the power source f2 are energized according to the image information p2 and p4, respectively. That will happen. Also at this time,
R2 and R4 of the heating resistor 8 are energized according to the image information p2 and p4, respectively. Further, at this time, R1 and R3 of the heating resistor 8 are not energized because the power source f1 is not supplied.

以上のような構成によれば、発熱抵抗体8を画情報に応
じて通電するためのシフトレジスタ4とデータラッチ5
と論理積回路4及びドライバ回路7などの各回路は、従
来の半分の数で構成することができる。また、読出制御
回路1や給電制御回路3はマイクロプロセッサ及びトラ
ンジスタなどで容易に構成できる。
According to the above configuration, the shift register 4 and the data latch 5 for energizing the heating resistor 8 according to image information are provided.
Each circuit such as the AND circuit 4 and the driver circuit 7 can be configured with half the number of conventional circuits. Furthermore, the read control circuit 1 and the power supply control circuit 3 can be easily constructed using a microprocessor, transistors, and the like.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、1走査線分の画素の複数
分の1のシフトレジスタとデータラッチと論理積回路及
びドライバ回路によって発熱抵抗体を駆動することによ
り、安価な装置を供給できるという効果がある。
As explained above, the present invention can provide an inexpensive device by driving a heat-generating resistor using a shift register, a data latch, an AND circuit, and a driver circuit each having a number of 1/multiple pixels of one scanning line. effective.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図及び第2図は本発明の一実施例のブロック図、及
び本実施例の動作を説明するためのタイの一例のブロッ
ク図及び従来例の動作を説明するためのタイミング図で
ある。 1・・・読出制御回路、2・・・ラインメモリ、3・・
・給電制御回路、4・・・シフトレジスタ(SL、S2
)、5・・・データラッチ(LL、R2)、6・・・論
理積回路(Al、A2)、7・・・ドライバ回路(DI
、D2)、8・・・発熱抵抗体(R1−R4)。
1 and 2 are a block diagram of an embodiment of the present invention, a block diagram of an example of a tie for explaining the operation of this embodiment, and a timing diagram for explaining the operation of a conventional example. 1... Read control circuit, 2... Line memory, 3...
・Power supply control circuit, 4...Shift register (SL, S2
), 5... Data latch (LL, R2), 6... AND circuit (Al, A2), 7... Driver circuit (DI
, D2), 8... Heat generating resistor (R1-R4).

Claims (1)

【特許請求の範囲】[Claims] 1走査線分の画素信号を記憶するラインメモリと、転送
クロックによって複数分の1に分割した前記画素信号を
記憶するシフトレジスタと、このシフトレジスタの出力
をデータラッチ信号によつて記憶保持するデータラッチ
と、このデータラッチの出力と印字命令信号との論理積
を求め出力する論理積回路と、この論理積回路の出力に
応じて発熱抵抗体に通電するドライバ回路と、分割した
前記画信号に対応する前記発熱抵抗体ごとに選択給電さ
せる給電制御回路と、前記転送クロックとデータラッチ
信号と印字命令信号を発生する読出制御回路とを有する
ことを特徴とする感熱記録装置。
A line memory that stores pixel signals for one scanning line, a shift register that stores the pixel signal divided into multiple parts by a transfer clock, and data that stores and holds the output of this shift register using a data latch signal. a latch, an AND circuit that calculates and outputs the AND of the output of the data latch and the print command signal, a driver circuit that energizes the heating resistor according to the output of the AND circuit, and A thermal recording device comprising: a power supply control circuit that selectively supplies power to each of the corresponding heat generating resistors; and a read control circuit that generates the transfer clock, data latch signal, and print command signal.
JP63129820A 1988-05-26 1988-05-26 Thermal recorder Pending JPH01299064A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63129820A JPH01299064A (en) 1988-05-26 1988-05-26 Thermal recorder

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63129820A JPH01299064A (en) 1988-05-26 1988-05-26 Thermal recorder

Publications (1)

Publication Number Publication Date
JPH01299064A true JPH01299064A (en) 1989-12-01

Family

ID=15019032

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63129820A Pending JPH01299064A (en) 1988-05-26 1988-05-26 Thermal recorder

Country Status (1)

Country Link
JP (1) JPH01299064A (en)

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