JPH0263373A - Thermo-sensing recorder - Google Patents

Abstract

PURPOSE:To decrease number of control circuits by providing a readout control circuit outputting a latch signal for each output of transfer clocks of a number being the division of one scanning line picture element number by number of times of readout, a shift register having number of stages being one over the number of times of readout of the number of picture elements of one scanning line and data latches of the same number as the shift register stage number. CONSTITUTION:Even number picture information sets p2, p4 in one scanning line transferred to shift registers S1, S2 are latched in data latches L1, L2 by using a data latch signal (c). The picture signal input by the succeeding one scanning line is attained to the shift registers S1, S2. When a print instruction signal (e) is supplied from a readout control circuit 1, data outputs d1, d2 of the data latches L1, L2 are ANDed with the print instruction signal (e) by AND circuits A1, A2. Only when the print instruction signal (e) is true and the data outputs d1, d2 are black level information, driver circuits D1, D2 drive heat resistors R2, R4 energized from a power supply f2. Thus, number of control circuit groups is halved than those of a convention recorder.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a thermal recording device used in facsimiles and the like.

Conventional thermal recording devices used in facsimiles and the like currently have shift registers with a number of stages corresponding to the number of pixels in one scanning line to be recorded. A common configuration is such that the heating resistor at the pixel position to be recorded is energized by driver circuits corresponding to the number of pixels.

FIG. 3 is a diagram showing an example of the configuration of such a conventional thermosensitive recording device, and FIG. 4 is a timing chart showing its control timing. For convenience of explanation, the number of pixels in one scanning line is assumed to be four.

In FIGS. 3 and 4, the input image signal a is input to the left end S1 of the shift registers S1 to S4, and is sequentially transferred to the right side as S1, S2, S3, and S4 by the transfer clock b of 1. When the transfer is completed, the image information p1-p4 for one scanning line transferred to each shift register 81-S4 is latched into data 1-L4 by the data latch signal C.

At this point, the shift registers 81 to S4 can receive image signals for the next scanning line.

The data outputs d1 to d4 of the data latches 1 to L4 are ANDed with the print command signal e by the AND circuits A1 to A4, and if the print command signal e is true and the data output di
Only when d4 is black information, the heating resistors R1 to R4 supplied with power by the power source f are energized by the driver circuits D1 to D4. For convenience of explanation, the number of pixels in one scanning line is assumed to be 4, but in reality, for example, in a thermal recording device that records on a 210 mm wide paper at a pixel density of 8 pixels/dragon, the number of pixels in one scanning line is 4. The number of pixels is as high as 1,680. Therefore, shift registers, data latches, AND circuits, and driver circuits as explained in FIG. 3 are generally mounted on one integrated circuit for every 64 pixels, for example.

Problems to be Solved by the Invention In such a conventional thermal recording device, a group of circuits such as a shift register, a data latch, an AND circuit, and a driver must be provided for each pixel constituting a scanning line. The present invention has been made in view of the above-mentioned conventional circumstances, and therefore the object of the present invention is to It is an object of the present invention to provide a new thermal recording device that eliminates the above-mentioned drawbacks inherent in the technology and can be constructed at a low cost.

Means for Solving the Problems In order to achieve the above object, a thermal recording device according to the present invention includes a line memory that stores image signals for one scanning line, and a line memory that stores image signals for one scanning line from the line memory. The signal is read out a certain number of times, and one pixel in the pixel period is output by changing the phase for each readout with a pixel period equal to the number of reading ratios from the read out image signal, and a transfer clock is generated for each output pixel. and a readout control circuit that outputs a latch signal every time the output of a transfer clock is the number of pixels in one scanning line divided by the number of readings, and the number of stages is one for the number of readings of the number of pixels in one scanning line. A shift register, a shift register that latches the data output of the shift register, a number of data latches that are the same as the number of register stages, and a shift register that takes the AND of the output of the data latch and a print command signal - logic that is the same as the number of register stages. a product circuit, a driver circuit of the same number as the number of shift register stages, which is commonly connected to the same number of heating resistor groups as the number of readings, and energizes the heating resistors according to the output of the AND circuit; and a driver circuit common to the driver circuit. and a power supply control circuit that selectively and separately supplies power to each heating resistor connected to each of the reading times.

EXAMPLE Hereinafter, an example of the present invention will be specifically described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 4 is a timing chart showing control timing in this embodiment. This embodiment is an example in which the same image signal is read out twice, and for convenience of explanation, the number of pixels in one scanning line is shown as four.

Referring to FIGS. 1 and 2, the readout control circuit 1 first reads out the image signals for one scanning line stored in the line memory 2, and the pixel period is equal to the number of times the same image signal is read out. One pixel, for example, an odd numbered pixel, is extracted from every two pixels and sent to the shift register S as an input image signal a.
], the left side of S2'@S1, and also supplies a transfer clock b that matches the pixel output timing, and sequentially transfers the input image signal a to S1, S2 and the right side. When half of the number of pixels in one scanning line has been transferred, that is, all odd numbered pixels in one scanning line have been transferred, the read control circuit il! 8] outputs a data latch signal C. Each shift l-register S
1゜Transferred to S2 - odd numbered stroke information p1 in the scanning line
, p3 are data latch L1, p3 by data latch signal C.
It is latched to R2. At this point, shift register S1,
R2 becomes capable of inputting an image signal for one scanning line for the next time.

On the other hand, the power supply control circuit 3 supplies power f1 to the odd-numbered heating resistors R1 and R3 after the -th image signal transfer is completed, and supplies power f2 to the even-numbered heating resistors R2 and R4. will be put on hold.

When the print command signal e is supplied from the read control circuit 1, the data outputs d1, d2 of the data latches L1, R2 are ANDed with the print command signal e by the AND circuits A1, A2, command signal e is true and data output d1,
Only when d2 is black information, the driver circuits D1 and D2 energize the heating resistors R1 and R3 that are supplied with power from the power source f1. As a result, the heating resistors R1 and R3 are energized according to the image information p1 and R3, respectively.

Further, at this time, the heating resistors R2 and R4 are not energized because the power source r2 is not supplied.

Next, the readout control circuit 1 reads out the image signals for one scanning line stored in the line memory 2 for the second time, extracts even-numbered pixels, and inputs them into the shift register S1 as an input image signal a.
It is input to the left end S1 of R2, and a transfer clock b matched with the pixel output timing is supplied to sequentially transfer the input image signal a to S1, R2 and the right side. When the transfer of half the number of pixels in one scanning line is completed, that is, when the transfer of all even-numbered pixels in one scanning line is completed, the read control circuit 1 outputs the data latch signal C. Even-numbered image information p2, R4 within one scanning line transferred to each shift register S1, R2 is latched into data latches L1, L2 by data latch signal C. At this point, image signals for the next scanning line can be input to R2 for each shift register.

On the other hand, after the second image signal transfer is completed, the power supply control device 3 supplies power f2 to the even-numbered heating resistors R2 and R4, and supplies power f1 to the odd-numbered heating resistors R1 and R3. Hold.

When print command signal 0 is supplied from read control circuit 1, data latch L1. The data outputs d1 and d2 of L2 are ANDed with the print command signal e by AND circuits A1 and A2, and if the print command signal e is true and the data outputs d1 and
Only when d2 is black information, the driver circuits D1 and D2 energize the heating resistors R2 and R4, which are powered by the power source f2. As a result, the heating resistors R2 and R4 are energized according to the image information p2 and R4, respectively. Further, at this time, the heating resistors R1 and R3 are not energized because the power source f1 is not supplied.

According to the above configuration, the number of control circuits such as shift registers, data latches, AND circuits, and drivers for energizing the heat generating resistors according to image information can be reduced to half of the conventional number. can.

Furthermore, the read control circuit or the power supply control circuit can be easily constructed using a microprocessor, transistors, and the like.

As described in detail, according to the thermal recording device of the present invention, it is possible to realize an inexpensive recording device with a reduced number of control circuits.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a thermal recording device according to the present invention, FIG. 2 is a timing chart showing its control timing, and FIG. 3 is a block diagram showing an example of the configuration of a conventional thermal recording device. FIG. 4 is a timing chart showing the control timing. 81~S...shift register, L1~L~data latch, A1-A4...AND circuit, D1~D4...
Driver, 1... Readout control circuit, 2... Line memory, 3... Power supply control circuit

Claims (1)

[Claims] A line memory that stores image signals for one scanning line, reads out the image signals for the same one scanning line from the line memory a certain number of times, and reads out the image signals that have been read out once at a pixel period equal to the number of times of reading. One pixel in the pixel period is output by changing the phase for each readout, and a transfer clock is generated for each output pixel, and a latch signal is generated every time a transfer clock is output, which is the number of pixels in one scanning line divided by the number of readouts. a readout control circuit that outputs a readout control circuit, a shift register having a number of stages equal to the number of readout times than the number of pixels of one scanning line, a data latch whose number is equal to the number of stages of the shift register that latches the data output of the shift register; A number of AND circuits that take the AND of the output of the data latch and a print command signal are connected in common to the number of stages of the shift register, and a group of heating resistors that is the same number as the number of times of reading, and heat is generated in accordance with the output of the AND circuit. comprising driver circuits of the same number as the number of shift register stages that energize the resistors, and a power supply control circuit that selectively and separately supplies power to each heating resistor commonly connected to the driver circuits for each number of readings. A thermal recording device characterized by: