JPH01304560A - Microprocessor bus monitor controller - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a control device using a microprocessor and a microprocessor bus monitoring and control device.

[Prior Art] As prior art to this invention, for example, Japanese Patent Application No. 59-15476 filed by the applicant on July 25, 1980
There is an invention of No. 1 "Microbroses Monitoring Device" (hereinafter referred to as "earlier application").

Figure 4 shows the structure of the invention of this earlier application. In the figure, (MP) is a microprocessor, (C1
) is a timer for measuring control timing, (Ml
) is a ROM constituting the program memory of the microprocessor (MP), (M2) is a RAM, and (M3) is a memory device; in the case of FIG. 4, a ROM is used. (Pl
) is the output port, (P2) is the input port, (AD) is the address signal line, (DT) is the data signal line, (ST) is the bus status signal line, (Do) is the output signal line, (DI) is the input The signal line (TR) is a trap signal line.

Note that the address signal line (AD) and data signal line (DT)
, and the bus status signal line (ST) will be referred to as a system bus or simply a bus in this specification.

Thailand? (C1), ROM (Ml), RAM (M2), output port (PL>, input port (P2), etc., each has an address signal line (AD).

The data signal line (DT) and bus status signal line (ST) are connected in parallel, so the same signal reaches all devices at the same time, but the address signal on the address signal line (AD) is Only when the address matches, the operation instructed by the signal on the bus status signal line (ST) is performed. Therefore, each device has its own address set.

Figure 6 shows that when the address signal is composed of 16 bits (there are 16 address signal lines (AD)) and the address is a 4-digit hexadecimal number and there are addresses from (0000)16 to (FFFF)+6, This is a memory map showing an example of addresses assigned to each device, and the address signals in the shaded areas are not used. In addition,
FIG. 5 is a flowchart showing the operation of the microprocessor (MP), and (10) to (15) indicate each step.

The operation of the apparatus shown in FIG. 4 will be explained below with reference to FIG. The microprocessor (MP) operates according to a program read from the ROM (Ml), and sends a signal representing the state of the controlled process to the input signal line (DI) and the input port.
) - (P2), process this to generate a control signal, store it in RAM (M2), and send it to the controlled object via the output port (Pl) and output signal line (DO). Output to a process is well known.

This microprocessor (MP) enters the initial state by turning on the power or by a reset signal, and step (10)
), after initializing the states of the RAM (M2) and the output port (Pl), the control operation is started. That is, step (
In step 11), the state of the controlled device is first fetched from the input port (P2), and a comparison process is performed with the control information stored in the RAM (M2) to determine the control signal to be sent to the output port (Pl). do. In the next step (12), the timing at which the control signal is sent to the output port (Pl) is determined based on the state of the output port (Pl) and the timer (C1).
When the sending timing is reached, a control signal is sent to the output port (Pl) (step (13)).
). After sending the control signal, the status of the input port (P2), RA
Based on the data of M (M2), it is determined in step (14) whether or not to continue the control. If the control is to be continued, the process returns to step (11), and if the control is to be terminated, the process is to step (15). and performs control termination processing.

However, if the value of the address signal on the address signal line (AD) becomes an abnormal value due to noise or the like, that is, the value shown in the diagonal line in FIG. A signal indicating an abnormal state is output, the operation of the microprocessor (MP) is interrupted, and depending on the situation, the control device and the controlled device are initialized, or the operation of these devices is stopped. This is ROM (Ml), RAM (
M2).

Invalid data is input by specifying a non-existent address to the input port (P2), etc., and the data is processed without realizing that it is invalid, resulting in damage to the microprocessor (MP), control device, and controlled device. It works abnormally or
This is to prevent the vehicle from running out of control.

[Problem to be solved by the invention] Since the conventional device is configured as described above, it is possible to prevent the microprocessor (MP) from running out of control, but it cannot deal with the following cases. There's a problem.

Figure 2 shows the output port (Pl) and input port (P2>
(hereinafter simply referred to as the boat) is an operation time chart showing the operation timing of the boat. In the figure, (P''AC) indicates the timing when the boat is being accessed, and (MAY) indicates the operating state of the microprocessor (MP). As shown in Figure 2, after giving the first command to the boat and before giving the next command, a recovery time is required until the influence of the first command disappears, but this recovery time is limited to the microprocessor. (MP) may be longer than one cycle of operation.In such a case, when the next command is given to the boat according to the operation cycle of the microprocessor (MP), a malfunction will occur.

In conventional technology, in order to deal with such cases, when accessing the same port consecutively, a meaningless dummy instruction, such as a "no" instruction, is inserted between two access instructions.
The solution is to write a program to insert commands such as ``operation'' and ``jump to next address,'' but it is troublesome to write a program while keeping these types of boats in mind, and the microprocessor (MP ) (in this case, this device is called the bus master), the problem cannot be solved programmatically.

This invention was made to solve the above-mentioned problems in conventional devices, and it is not only possible to monitor and control a microprocessor (MP), but also to monitor and control all devices connected to a system bus. The purpose is to provide a device that can.

[Means for Solving the Problems] The device according to the present invention monitors the signals on the address signal line and the signals on the bus status signal line, and monitors the signals on the address signal line and the bus status signal line for a predetermined period of time from the time when these signals reach a preset value. , we decided to control the bus mask to open the system bus.

[Operation] In this invention, when a boat is accessed, the system bus maintains its state until the boat recovers, so that malfunctions will not occur even if the boat is subsequently accessed. .

[Examples] Examples of the present invention will be described below with reference to the drawings. 1st
The figure is a block diagram showing one embodiment of the present invention. In the figure, the same reference numerals as in FIG. 4 indicate the same or corresponding parts.
) is a comparison circuit, and (TM) is a timer circuit.

The comparator circuit (CP) is set with the addresses of the output port (PL) and input port (P2) (see Figure 6) and codes representing access commands to these ports.
When the signal on the address signal line (AD) matches the address of these boats and the signal on the bus status signal line (ST) is an access command to these boats, the comparison circuit (cp) detects the match signal. It outputs and controls the timer circuit (TM). The timer circuit (TM) is set by this control, and is automatically reset after a preset time has elapsed from the time of setting.

FIG. 3 is an operation time chart showing the operation of this timer circuit (TM), where the same symbols as in FIG. 2 indicate the same or equivalent signals, and (TMO) indicates the output waveform of the timer circuit (TM). If the input of the clock signal to the microprocessor (MP) is blocked during the period when (TMO) is at logic "L",
Since the microprocessor (MP) stops operating during this period, the boat recovers to a state in which it can accept the next command during this halt period, and there is no need to be aware of the boat's recovery time in the program.

In the above embodiment, the boat is monitored by the comparator circuit (CP), but it is easy to configure it to monitor other devices as well, and the comparator circuit (CP) in FIG. It is also possible to configure a device that achieves both objectives by using the memory device (M3) shown in the figure.

[Effects of the Invention] As explained above, this invention utilizes a microprocessor (
The system bus status of MP) is monitored, and when the boat is accessed, the bus master is made to release the system bus for a predetermined period of time. This allows time for the boat to recover, and even if the boat is accessed subsequently, This has the effect of eliminating malfunctions.

[Brief explanation of the drawing]

1 is a block diagram showing an embodiment of the present invention, FIG. 2 is an operation time chart showing the operation of the output port and input port shown in FIG. 1, and FIG. 3 is a time chart showing the operation of the timer circuit shown in FIG. 4 is a block diagram showing the configuration of a conventional device; FIG. 5 is a flowchart showing the operation of the microprocessor shown in FIG. 4; and FIG. 6 is a memory map showing address allocation. (MP) is a microprocessor, (AD) is an address signal line, (ST) is a bus status signal line, (Pl) is an output port, (P2) is an input port, (CP) is a comparison circuit, (T
M) is a timer circuit. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Scope of Claims] A microprocessor bus monitoring and control device that is attached to a control device using a microprocessor and monitors the state of a system bus of the microprocessor and performs necessary control, comprising: an address signal line of the system bus; A comparison circuit that inputs the address signal of the address signal and the signal on the bus status signal line and outputs a match signal when these signals match a preset value. A microcontroller comprising: a timer circuit that is reset after a preset time has elapsed; and means for controlling a bus master that manages the system bus to open the system bus while the timer circuit is in the set state. Processor bus monitoring control device.