JPH01304579A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce the circuit area independently of the number of accumulated data by converting the data rate of input data so that the number of input data and the number of accumulated data are equalized. CONSTITUTION:Input data is inputted to an n-bit register 3 from an input terminal 1, and the data rate is converted by an m-bit register 4. A one-bit adder 6 adds input data of the m-bit register 4 and accumulated data of the m-bit register 5 bit by bit. Carry of this adder 6 is outputted to a one-bit register 7. The addition output of the one-bit adder 6 is outputted through an m-bit register 5.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit that performs cumulative addition using serially input data, a so-called cumulative adder.

[Conventional technology]

Conventionally, this type of accumulative adder has a basic configuration as shown in FIG. It is configured to cumulatively add serially input input data and cumulative data.

In Fig. 2, 1 is an input terminal for serially inputting input data, 2 is an output terminal for serially outputting accumulated data, and Ao%An-, represents n-bit input data, so "5m -1 Ham human cumulative data are shown respectively.

Next, the operation will be explained.

First, input data A of n bits is input from input terminal 1.

~An-, is serially input to the n-bit register 10. Then, the output of the register 10 for each bit is m
It is input to one input terminal of the bit adder 12. That is, data A is serially input. -Ayl-1 is
The n bits are input in parallel to one input terminal of the m bit adder 12. Here, it is assumed that "0" is input to one input terminal of the m-bit adder 12 of (m-,) bits.

Furthermore, m-bit cumulative data So-8m-1 is input to the other input terminal of the m-bit adder 12, and this adder 12 performs cumulative addition of the input data and the cumulative data. The output of the m-bit adder 12 is input to the m-bit register 11 as accumulated data. The above operations are repeated to perform cumulative addition of input data. Note that after this cumulative addition is completed, the accumulated data is serially output from the m-bit register 11 to the output terminal 2, and at the same time, the m-bit register 11 is reset to O.

[Problem to be solved by the invention]

However, since the conventional cumulative adder is configured as described above, an adder corresponding to the number of accumulated data is required, and as the number of accumulated data increases, the circuit area of the semiconductor integrated circuit increases. Ta.

The present invention has been made in order to solve the above-mentioned problems, and provides a semiconductor integrated circuit that can reduce the circuit area regardless of the amount of accumulated data by cumulatively adding serially input data bit by bit. The purpose is to provide circuits.

[Means to solve the problem]

The semiconductor integrated circuit according to the present invention performs cumulative addition using a 1-bit adder and a 1-bit register by converting the data rate of serially input data to make the number of input data equal to the number of cumulative data. This is what I decided to do.

[Effect]

The semiconductor integrated circuit of the present invention can perform cumulative addition using a 1-bit adder and register by converting the data rate of input data so that the number of input data and the number of cumulative data are the same. The area becomes smaller.

〔Example〕

Hereinafter, the present invention will be described in detail based on embodiments shown in the drawings.

FIG. 1 is a block diagram showing the basic configuration of an accumulative adder according to an embodiment of the present invention. In the figure, 1 is an input terminal for inputting input data in 7 reals, 2 is an output terminal for serially outputting accumulated data, 3 is an n-bit register for input data, and 4 is an input terminal for this register 3. m for converting the data rate of stored input data
It is a bit register. Further, 5 is an m-bit register for cumulative addition output of a 1-bit adder to be described later, and 6 is 1 for cumulatively adding the input data of the m-bit register 4 and the cumulative data of the m-bit register 5 bit by bit. The bit adder T is a 1-bit register for the carry output of this 1-bit adder 6. In addition, AO-An-
1 indicates n-bit input data, and so-sm-1 indicates m-bit accumulated data.

Next, the operation of the configuration of the above embodiment will be explained. Here, to simplify the explanation, it is assumed that the input data is n bits and the cumulative data is NXn (=m) bits (N=1.2
,3.・1”・any integer). First, n bits of input data Ao-A41-x are serially input from input terminal 1.
Input to bit register 3. Then, the output of register 3 for each bit is N for converting the data rate.
Xn (=m) is input to the bit register 4. That is, serially input data Ao to An-1 is input to the Nxn (=m) pit register 4 in n-bit parallel fashion. Here, the upper (N-t) n bits from An to Am of the NXn (=rrl) pit register 4 are "0".
” is entered.

The NX n (=r11) pit register 4 serially inputs data from Ao to Am- to one input end of the 1-bit adder 6 at a data rate N times the input data. That is, by multiplying the data rate of n-bit input data by N times, the data rate of n-bit input data is NX n
(=m) bits of data (upper (N-1) n
The bit can be input to the 1-bit adder 6 as "0" is input. Also, the 1-bit adder 6
NX n (-m) bits of cumulative data So to Sm- are serially input to the other input terminal of the adder 6, and the adder 6 performs cumulative addition of the input data and the cumulative data bit by bit. Here, the carry output of the 1-bit adder 6 is input to the 1-bit register 7, and the carry output of the 1-bit adder 6 is taken when performing cumulative addition with the next bit. Then, the output of the 1-bit adder 6 is NXn (=m
) Serially input to the pit register 5 as cumulative data. The above operations are repeated to perform cumulative addition of input data.

Note that after this cumulative addition is completed, the cumulative data is NXn (=
m) The data is serially output from the pit register 5 to the output terminal 2, and at the same time, the Nxn (=m) pit register 5 and the 1-bit register 7 are reset to 0.

〔Effect of the invention〕

As described above, according to the present invention, data rate-If conversion of input data is performed so that the number of input data and the number of accumulated data are the same, and cumulative addition is performed using a 1-bit adder and a 1-bit register. Therefore, cumulative addition can be performed for each bit, which has the effect of reducing the circuit area of the semiconductor integrated circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a semiconductor integrated circuit according to the present invention, and FIG. 2 is a block diagram showing a conventional cumulative adder. 1...Input terminal, 2...Output terminal, 3...@
n-bit register, 4... m-bit register, 5...
...ejrl bit register, 6...1 bit adder, T...1 bit register, An~A low, -0
...Input data, Sosm-. ...cumulative data.

Claims (1)

[Claims] A multi-bit register for converting the data rate of serially inputted input data, a 1-bit adder for cumulatively adding the input data and accumulated data stored in this register bit by bit, and this adder. A semiconductor integrated circuit comprising: a 1-bit register for carry output; and a multi-bit register for cumulative addition output of the 1-bit adder.