JPH01307972A - Pulse processing circuit - Google Patents

Abstract

PURPOSE:To correctly detect and reproduce an information signal even of an abnormal signal is generated by driving a reset pulse generating circuit by a set pulse and outputting a pulse for resetting a flip-flop circuit after a prescribed time or above has elapsed. CONSTITUTION:A reset pulse generating circuit 12 inputs a set pulse S1 being an output of a comparator 9, and outputs a pulse S3 which can reset an FF circuit 11 after a prescribed time or above has elapsed. An OR. circuit 13 inputs the output S3 of a reset pulse generating circuit 12 and a reset pulse S2 being an output of a comparator 10, and executes an OR operation of them. ¦Subsequently, its output S4 is inputted to a reset terminal of the FF circuit 11. In such a way, even if a minute abnormal signal is generated due to a flaw on the surface, etc., of an information recording medium, and a signal having only a set pulse is inputted to a flip-flop circuit, the flip-flop circuit can be reset, and even if an abnormal signal is inputted, a malfunction does not occur.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a pulse processing circuit that processes pulse signals, and is particularly suitable for processing pulse signals containing information from an information recording medium. 0 [Prior Art] FIG. 5 is a block diagram of an information signal processing circuit that processes an information signal from an information recording medium using a conventional pulse processing circuit shown in Japanese Patent Application No. 62-220297, for example.
In the figure, (1) indicates the information signal obtained by irradiating the information recording medium (not shown) with a laser beam (not shown).
A filter circuit that removes noise components outside the required band (
2) is a first stage amplifier that amplifies the information signal by a predetermined magnification, (
3) is the amount of signal attenuation, that is, the amount of attenuator 3, depending on the recording position of each information signal on the information recording medium (not shown).
(4) is an attenuator circuit that adjusts A to make the magnitude of all information signals almost constant; an automatic gain control amplifier (hereinafter referred to as an AGC amplifier) for maintaining the magnitude of the information signal at a constant value even in response to changes in output, changes in reflectance of an information recording medium (not shown), etc.; (5) is a differentiation circuit that differentiates the constant output signal (4aA) from the AGC amplifier (4), and (6) is the beginning of the information signal by inputting the output signal (5aA) of the differentiation circuit (5). This is a header detection circuit that outputs a pulse (6aA) corresponding to information on a part of the header, and is configured using a conventional pulse processing circuit. (7) is the add-on data detection I that detects the information signal of the part called the add-on data part following the above header part.
n, (8) is the output of the add-on data detection circuit (7aA)
〇No. 6, which is a pulse generation circuit that generates pulses in response to
The figure is a detailed configuration diagram of the header detection circuit (6),
(9) is a comparator that compares the magnitude of the input signal (5aA) and the reference signal v1 and outputs the set pulse signal S1, and 00 compares the magnitude of the input signal (5aA) and the reference signal V2. The comparator αη that outputs the reset pulse signal St is a flip-flop circuit (hereinafter referred to as (referred to as an FF circuit), and B indicates a pulse output.

FIG. 7 is a detailed configuration diagram of an information signal obtained from an information recording medium (not shown), which consists of a portion called a header portion (c) and a portion called an add-on data portion (g). Part (c) of the header further includes a sector mark to help synchronize the signal frequency and an address that records the recording position on the information recording medium (not shown) to facilitate signal processing. These are recorded in advance on an information recording medium (not shown).

Add-on data section 0 consists of a flag section indicating whether information data is recorded, a pre-angle section provided to increase the processing speed of information data, and an information data section. This is a portion that is additionally recorded on an information recording medium (not shown) by a recording device (not shown).

Also, before the header part (6) and the add-on data part (g)
After , there is a gap where no information data is recorded.

FIG. 8 is a waveform diagram of the information signal mentioned above, where the horizontal axis is time and the vertical axis is voltage. The signal waveform of the header part (c) is approximately I
MHz, the signal waveform of the add-on data section (G) is several MHz
It has a frequency of z.

FIG. 9 is an enlarged view of FIG. 8 and a waveform diagram for explaining the operation of the circuit in FIG. FIG. 3 is a waveform diagram for explaining the operation.

The information signal processing circuit using the conventional pulse processing circuit is configured as described above, and the information signal obtained from the information recording medium (not shown) is passed through the filter circuit (1) in FIG.
The noise components are removed through the first stage amplifier (2), the attenuator circuit (3) and the AGC amplifier (4).
) to output an output signal (4aA) adjusted to a constant magnitude. A differentiating circuit (5) differentiates this and sends a differentiated output signal (5aA) shown in FIG. 9 to a header detecting circuit (6) and an add-on data detecting circuit (7). The header detection circuit (6) has a differential output signal (5aA)
The bipolar peak portions of the waveform are detected and a pulse output signal (6aA) shown in FIG. 9 is output. By comparing this with the reference signal, the information signal of the header part (9) is detected,
Reproduce. On the other hand, the add-on data detection circuit (7) detects a predetermined level (9th level) of the waveform of the differential output signal (5aA).
Detects the part above the third comparator level 2) in the figure,
A pulse output signal (7aA) corresponding to this portion is output.

The pulse generating circuit (8) receives this signal and generates this signal (7a
The pseudo pulses based on noise are removed from A), and only the pulse signal based on the information signal of the add-on data section (g) is output.

Next, the details of the operation of the header detection circuit (6) in which a conventional pulse processing circuit is used are shown in FIGS. 6 and 10.

This will be explained based on FIG. In Fig. 6, input signal 5
Given a8, comparators (9) and 60)
is the magnitude of this signal 5aA as the reference signal V1. When the signal 5aA is larger than the reference signal v1, the comparator (9) outputs the set pulse S1 at H level, and when the signal A is smaller than the reference signal ■, the comparator α0 outputs the set pulse S1. Outputs an H level reset pulse S2. This set pulse S1 is converted to S(
When the reset pulse S is inputted to the R (reset) terminal, the FF circuit αυ generates a pulse, and when the reset pulse S is inputted to the R (reset) terminal, the generation of this pulse is stopped. That is,
The output (5aA) of the FF circuit αυ is output only from the set pulse S1 to the reset pulse S, and has an output waveform B as shown in FIG. In other words, when eight set pulses at H level are input, the output B of the FF circuit 0° C. becomes H level, and when the reset pulse S at H level is input, output B changes to L level.

[Problem to be solved by the invention]

In the information signal processing circuit using the conventional pulse processing circuit as described above, due to scratches on the surface of the information recording medium (not shown), the gaps in the information signal (see FIG. 7) may be affected as shown in FIG. 11. When such a minute abnormal signal A1 is generated, the output (5aA) of the differentiating circuit (5) produces an abnormal waveform A as shown in FIG. That is, the input 5aA of the header detection circuit (6) is larger than the reference signal vi due to the abnormal waveform A2, but does not become smaller than the reference signal ■, so the comparator Q0 outputs an H level reset pulse S2.
is not output, and therefore the pulse output B of the FF circuit συ has an abnormally long duration. Information signals are detected and reproduced by comparing the duration of pulse output B with the duration of a reference signal, so if the above phenomenon occurs, the information signal cannot be detected or reproduced correctly. The problem was that it created fear.

The present invention has been made to solve this problem, and an object of the present invention is to provide a pulse processing circuit constituting an information signal processing circuit that can correctly detect and reproduce an information signal even if an abnormal signal occurs.

[Means to solve the problem]

A pulse processing circuit according to the present invention includes a flip-flop circuit to which a pulse pair consisting of a set pulse and a reset pulse that follows after a predetermined time is input, and a reset pulse generation circuit driven by the set pulse. It is something that

[Effect]

In this invention, the reset pulse generation circuit is driven by the set pulse and outputs a pulse for resetting the flip-flop circuit after the predetermined time period has elapsed.

〔Example〕

1 and 2 show an example in which the pulse processing circuit according to the present invention is applied to an information signal processing circuit that processes information signals from an information recording medium (not shown). The circuit block diagrams (1) to (5) are the same as the conventional circuit shown in FIG. (6A) is a header detection circuit to which the pulse processing circuit according to the present invention is applied, and is configured as shown in FIG. That is,
In FIG. 1, comparator (9) and α0. The FF circuit Qη is similar to the conventional one. @ is a pulse S that inputs the set pulse S1 which is the output of the comparator (9) and can reset the FF circuit αυ after a predetermined time has elapsed.
, the reset pulse generation circuit αT inputs the output S3 of this reset pulse generation circuit (2) and the reset pulse St which is the output of the comparator αQ,
This is a logical sum (OR) circuit that performs these logical sum operations, and its output S is configured to be input to the R (reset) terminal of the FF circuit αυ.

FIG. 3 is a circuit diagram showing a specific configuration of the above-mentioned reset pulse generation circuit @, where α→ is a one-shot circuit that inputs the set pulse Sl and generates the pulse pair S and S, and Q! 19 and αQ are a resistor and a capacitor connected to the one-shot circuit α→, and these are for determining the pulse width of the pulse S output from the Q terminal of the one-shot circuit a<. 07) is a filter circuit connected to the Q terminal and consisting of a resistor and a capacitor, and is used to smooth the rise and fall points of the pulse S. (E) is a logical product (AND) circuit which inputs the output S of this filter circuit aη and the output S6 from the inverting output terminal Q of the one-shot circuit (14) and performs a logical product operation of these;
Its output is pulse S3.

In the information signal processing circuit configured and configured as described above,
Filter circuit (1) and first stage amplifier (2) shown in Figure 2
, the attenuator circuit (3), the AGC amplifier (4), and the differentiator circuit (5) are the same as the conventional ones, and will therefore be omitted.

Now, a signal 5aA having an information signal obtained from an information recording medium (not shown), that is, the output of the differentiating circuit (5) shown in FIG. 5, is input to the header detection circuit (6A) shown in FIG. 1. . When this signal 5aA is a normal signal as shown in FIG. 10, the operation of the header detection circuit (6A) is the same as in the conventional case. That is, comparator (9), QO
As a result, an H-level set pulse S and an H-level reset pulse S2 are output after a predetermined time, and are sent to the R terminal of the FF circuit αυ through the S terminal and the OR circuit a3, and the FF circuit αυ A pulse output 5aA as shown in FIG. 10 is generated. This is a logical sum circuit (13 is
This is because if an H level signal is input, the input signal will output either S or S.

Further, after the above-mentioned predetermined time has elapsed since the input of the set pulse S1, the reset pulse generation circuit (6) is activated to the FF circuit 0.
A pulse S, which can reset υ, is generated, and this pulse S
, are H-level signals, so they pass through the OR circuit (to), but this pulse S3 is already input once after the reset pulse S2 is input to the FF circuit αυ, so no problem occurs. This is because these pulses S5. S,
This is because both are signals that stop the generation of the output 6aA of the FF circuit αη.

Next, due to scratches on the surface of the information recording medium (not shown),
A slight abnormal signal is generated in the jump part (see Fig. 7) of the information signal, which should not originally have a signal component, and therefore an abnormal signal A1 as shown in Fig. 4 is input to the header detection circuit (6A). Explain when to do so. FIG. 4 is a waveform diagram for explaining the operation of the header detection circuit (6A) and the reset pulse generation circuit @ constituting the header detection circuit (6A).

The abnormal signal A shown in FIG. 4 has the reference signal V! at its beginning. There is no point where it is smaller than. Therefore, the comparator (10) shown in Figure 1 does not output the H-level reset pulse S! at this point. However, the one-shot circuit (14) of the reset pulse generation circuit (6) Upon receiving the pulse St,
A pulse S is simultaneously output from the Q terminal, and a pulse S6, which is an inverted output of S, is output from the Q terminal. The width of these pulses is selected to be the optimum width depending on the resistance (to) and capacitor (IIO value).The filter circuit αη functions to smooth the rising and falling points of the pulse S, The pulse S is changed into eight pulses with a smoother waveform. Both this pulse S7 and the inverted output pulse S6 are connected to the AND circuit (1).
sent to.

The AND circuit (1) detects a common output point of both of these pulses and outputs the pulse S3 at this point. This H-level pulse S3 passes through the OR circuit α and then passes through the FF circuit Qυ(7
) R (input to the IJ upper set terminal to stop the generation of output B of the FF circuit αυ. Therefore, the output 6aA of the FF circuit (6) is shown in Fig. 4, which is almost the same as when a normal signal 5aA is input. Since the information signal from the information recording medium (not shown) is detected and reproduced by comparing this waveform with the reference signal, no problem occurs.In other words, the information signal having the configuration shown in FIG. Part of the header (c) can be detected and played correctly.

Detection and reproduction of the add-on data section (g) in FIG. 7 are the same as in the conventional case.

In addition, in the above embodiment, as an example of the configuration of the reset pulse generation circuit @, a case was shown in which the reset pulse generation circuit @ was composed of a function circuit α→, a filter circuit α, and an AND circuit, but it is also possible to use a frequency dividing circuit of a counter circuit , a shift register circuit, etc. may be used. That is, set pulse S1
After a predetermined period of time has elapsed after the reset pulse S
It is only necessary to construct a circuit that generates a pulse S equivalent to .

〔Effect of the invention〕

As explained above, the pulse processing circuit according to the present invention has the following features:
A flip-flop circuit receives a pulse pair consisting of a set pulse and a reset pulse, and a reset pulse generation circuit outputs a pulse driven by the set pulse to reset the flip-flop circuit. Even if an abnormal signal is input to the flip-flop circuit, the flip-flop circuit can be reset. Therefore, when used for signal processing including information from an information recording medium, for example, there is no malfunction even if an abnormal signal is input. There is.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of a header detection circuit using a pulse processing circuit according to an embodiment of the present invention, Fig. 2 is a block diagram of an information processing circuit using the circuit of Fig. 1, and Fig. 3 is a reset pulse generation circuit. A detailed circuit configuration diagram of the circuit, FIG. 4 is a waveform diagram for explaining the operation of FIGS. 1 and 3, FIG. 5 is a block diagram of a conventional information processing circuit, and FIG. 6 is a diagram using a conventional pulse processing circuit. 7 is a detailed configuration diagram of the information signal, FIG. 8 is a waveform diagram of the information signal shown in FIG. 7, and FIG. 9 is a diagram for explaining the operation of the circuit in FIG. 5. Waveform diagram, 10th
This figure and FIG. 11 are waveform diagrams for explaining the operation of the header detection circuit shown in FIG. 6. In the figure, OI) is a flip-flop circuit, and (6) is a reset pulse generation circuit. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] (1) A flip-flop circuit to which a pulse pair consisting of a set pulse and a reset pulse that follows after a predetermined time is sequentially input, and is driven by the set pulse,
A pulse processing circuit comprising: a reset pulse generation circuit that outputs a pulse after the predetermined time has elapsed and resets the flip-flop circuit with the output pulse.