JPH0384777A - Margin warrant circuit for readout data - Google Patents

Abstract

PURPOSE:To discriminate a margin to an amplitude detection and a margin to phase discrimination simultaneously by providing an attenuation circuit, subtraction circuit, a filter circuit, a level detection circuit, a peak detection circuit, an AND circuit and a phase discrimination circuit. CONSTITUTION:When a control signal fed from a signal line 107 to an attenuation circuit 10 is a signal of the operating mode, an AGC output signal is attenuated by the attenuation circuit 10 and outputted. A subtraction circuit 5 subtracts the attenuation signal outputted from the attenuation circuit 10 from the output signal outputted from an AGC circuit 4. Thus, the amplitude of the output signal to the signal line 102 is decreased and the peak point of the output signal is ambiguous. Then the readout signal is subtracted from the readout signal based on the signal attenuated by a prescribed value at the attenuation circuit at the warrant test of the readout operation in this way, it is possible to discriminate simultaneously the margin to the amplitude detection and the margin to the phase discrimination.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a read data margin guarantee circuit that guarantees the read margin of data in a magnetic storage device or the like.

(Prior Art) Conventionally, in this type of magnetic storage device, the following two methods are known as methods for guaranteeing read data margin.

The first method consists of a level detection circuit 7 and a variable resistor 11, as shown in FIG. Level detection circuit 7
A readout signal is applied to one input terminal of the variable resistor 11 via a signal line 201, and a sliding terminal voltage of the variable resistor 11 is applied to the other input terminal of the variable resistor 11 via a signal line 202. The variable resistor 11 has one terminal applied with a voltage ``2'' and the other terminal grounded.

Figure 5 shows the waveforms of the signals on each signal line shown in Figure 4.0 During normal operation, the variable resistor 1
The amplitude of the read signal of the signal line 201 is detected using the output voltage V from 1 as the threshold voltage. During the read signal margin guarantee test, the variable resistor 11 is adjusted to set the threshold voltages to the values of v2 and v. Thereby, the read margin can be guaranteed against the pseudo peak r and the amplitude drop S due to minute defects appearing in the read signal on the signal line 201. First, when the threshold voltage is 3, the output signal on the signal line 203, which is the output of the level detection circuit 7, is as follows. That is, the output pulse S0 corresponding to the portion of the amplitude decrease S in the readout signal on the signal line 20i is extremely fine as shown by the broken line, indicating that it is close to the detection limit. Next, when the threshold voltage is V2, it shows that there is still some margin for the pseudo peak r.

In the second method, as shown in FIG.
and a delay line 13. A read clock is inputted to one input terminal of the data discrimination circuit 12 via the signal line 301, and the other input terminal is inputted to the signal line 301.
The output signal of the delay line 13 is inputted through the line 03. Furthermore, a data pulse obtained by pulsing a read signal is input to an input terminal of the delay line 13 via a signal line 302. The delay amount of the delay line 13 can be set to different time values by switching the output terminals t1 to ts.9 During normal operation, the delay amount of the delay line 13 is set to 1+. This amount of delay is the position with the most margin for data discrimination. In the case of a read operation guarantee test, the delay amount of the delay line 13 is set to the values t2 and t.

FIG. 7 is a waveform diagram showing waveforms at various parts in FIG. 6. As shown in FIG. 7, from the delay line 13 to the signal line 303
The leading edge of the data pulse, which is the output signal to the signal, [30
rH of the read clock on 1.

If the signal line 301 is located in the rrfJ band when the level is
Data discrimination circuit 1 is synchronized with the trailing edge of the upper read clock.
2 generates an output signal pulse on signal line 304. Otherwise, the pulse is not generated. In other words, the data discrimination circuit 12 distinguishes the phase of the data pulse on the signal line 303 that includes a peak shift caused by interference between reproduced waveforms and a defect in the recording body. Synchronization is achieved using read clocks on different signal lines 301. A well-phased output data pulse is then generated on signal line 304.

During the guarantee test, the delay amount of the delay line 13 was set to t.
2, the phase of the data pulse on signal 1303 is t
Move forward relatively by +ti.

At this time, pulse P of the data pulses on the signal line 303
I protrudes from the rH region of the rising clock on the signal line 301, making it impossible to discriminate the data. Conversely, when the delay amount of the delay line 13 is set to t3, the phase of the data pulse on the signal line 303 is relatively delayed by the time t31+, and data discrimination is guaranteed for the pulse P□.

As described above, the second method guarantees margin for phase discrimination of data pulses on the signal line 303.

(Problem II to be Solved by the Invention) As described above, the conventional read operation guarantee system has the following problems to be solved.

There are currently two recording modulation methods used in magnetic storage devices.
-7 code and 1-7 code are the mainstream. Since the signal detection of these codes has a small operating margin for phase discrimination and a small margin for amplitude detection, it is necessary to guarantee both phase discrimination and amplitude detection.
Guarantee testing takes a lot of time.

Further, the threshold voltage and delay time for the guarantee test are automatically set between the magnetic storage device and the host device or test device via the control signal line. However, even in this case, the amount of hardware in the control circuit increases, reducing the reliability of the entire system.

(Means for Solving the Problems) In order to achieve the above object, the read data margin guarantee circuit of the present invention amplifies the signal read from the medium by the magnetic head to a predetermined level using an automatic gain control circuit. In a read data merging guarantee circuit that tests the margin of amplitude with respect to a threshold signal and the margin of phase discrimination with respect to a read clock with respect to a read signal obtained by an attenuation circuit that generates a signal, a subtraction circuit that generates a subtraction signal by subtracting the value of the attenuation signal from the value of the read signal, and a filter signal that generates a filter signal by removing frequency components below a predetermined frequency from the subtraction signal. a level detection circuit that compares the filter signal with the threshold signal and generates a level detection signal when the level of the filter signal is higher than the level of the dark value signal; a peak detection circuit that generates a peak signal when the maximum value is detected; an AND circuit that performs an AND of the level detection signal and the peak signal and outputs an AND signal; and a phase discrimination circuit for detecting a phase margin with respect to the read clock.

(Example) Next, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the read margin guarantee circuit according to the present invention. an amplifier 3 for amplifying the recorded signal reproduced by the amplifier 3; and a signal line 10 by the amplifier 3.
An automatic gain control circuit (hereinafter referred to as AGC circuit) 4 that amplifies the readout signal output to the signal line 107 to a predetermined average amplitude, and attenuates the output signal from the AGC circuit 4 based on the control input signal on the signal line 107. Attenuation circuit 10 and AGC
A subtraction circuit 5 that subtracts the output signal of the attenuation circuit 10 from the output signal of the circuit 4, and a filter circuit 6 that inputs the subtracted signal of the signal line 102 to remove low frequency signals and perform equivalent processing. , from the filter circuit 6 to the signal line 103
A level detection circuit 7 compares the output signal outputted above with a threshold voltage vth and outputs an output pulse for an amplitude larger than Vth; Generated peak detection circuit 8
and an AND gate circuit 9 that performs an AND operation on the output signal outputted onto the signal line 104 by the level detection circuit 7 and the output signal outputted onto the signal line 105 from the peak detection circuit 8.

FIGS. 2 and 3 are waveform diagrams showing waveforms at various parts in FIG. 1, respectively. FIG. 2 shows waveforms when the attenuation circuit 10 is not in operation, and FIG. 3 shows waveforms when the attenuation circuit 10 is in operation.

Next, based on FIG. 2, the operation when the attenuation circuit 10 is inactive in the embodiment of FIG. 1 will be explained.

When the control signal applied to the attenuation circuit 10 from the signal line 107 indicates the non-operation mode, the attenuation circuit 10 does not operate.
The pseudo peak x0 and amplitude drop y0 caused by the above defects are
The output signals outputted from the filter circuit 6 onto the signal line 103 are respectively X l and 3/ (However,
Since there is a margin for detection with respect to the threshold voltage vth,
In the output signal from the level detection circuit 7 to the signal line 104, there is no pulse at the position X) corresponding to the pseudo peak x1. Furthermore, a pulse y is generated at a position corresponding to the amplitude decrease y2. The output signal output from the peak detection circuit 8 onto the signal line 105 and this pulse y.

is ANDed by the AND gate circuit 9 and output as the output signal y on the signal line 106. Among the bits included in the output signal from the AND gate circuit #19 to the signal 41106, the peak Pulse Z+ including shift
The +Z2+Zs bit is in the l'HJ region of the read clock (RC) generated by the data discrimination circuit 12 at the subsequent stage, and it is possible to discriminate the data.

Next, if the control signal applied from the signal line 107 to the attenuation circuit 10 is an operation mode signal, the AGC output signal is attenuated by the attenuation circuit 10 and output. The waveforms of each part at this time are as shown in FIG. The subtraction circuit 5 subtracts the attenuation signal output from the attenuation circuit 10 from the output signal output from the AGC circuit 4. Therefore, signal line 1 in FIG.
The amplitude of the output signal to 02 is reduced and the peak point of the output signal becomes vague. Pseudo peak XoJ included in read signal? ? The amplitude reduction y0 becomes the signal X 12+V'□ in the output signal of the filter circuit 6. Since the signal XI2 has a margin with respect to the threshold voltage vth, no pulse is generated in the output signal from the level detection circuit 7 to the signal 11104. Since the amplitude of the signal y12 is lower than that of vth, the pulse on the signal line 104 disappears. As a result, from the AND gate circuit 9 to the signal line 106
No pulse is generated at position yI4 corresponding to signal yI2 of the output signal to , and normal reading becomes impossible. Therefore, it can be seen that the read operation margin of this magnetic storage device is small. In addition, since the peak point of the output signal of the subtraction circuit 5 becomes vague, the signal line 1 is connected to the peak detection circuit 8.
The bits included in the output signal to the signal line 106 have large fluctuations, and the bits included in the output signal to the signal line 106 that have large fluctuations include many peak shifts, z, , z, 2. Z is the data discrimination circuit 12 in the subsequent stage
When compared with the rH region of the read clock (RC) generated in bits Zr, Z2 . Zs often deviates from the "H" region, making normal reading impossible. Therefore, the read operation margin of the present device can be determined here as well.

As described above, by subtracting a signal obtained by appropriately attenuating the read signal from the read signal, it is possible to simultaneously determine the margin for amplitude detection and the margin for phase discrimination.

(Effects of the Invention) As explained above, the read data margin guarantee circuit of the present invention uses the attenuation circuit to attenuate the read signal by a predetermined value from the original read signal during the read operation guarantee test. Subtract. Therefore, it becomes possible to simultaneously determine the margin for amplitude detection and the margin for phase discrimination.

Therefore, if the read margin guarantee circuit of the present invention is adopted, a control circuit that switches the threshold value when testing the signal amplitude margin or a control circuit that switches the delay amount when testing the phase discrimination margin becomes unnecessary. At the same time, control becomes easier. Further, the read guarantee test can be performed easily and in a short time, and the reliability of the device can also be improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention. FIGS. 2 and 3 are diagrams explaining the operation of the embodiment of FIG. 1. FIG. 4 is a block diagram of a conventional amplitude margin detection circuit. , FIG. 5 is a diagram explaining the operation of the circuit in FIG. 4, FIG. 6 is a block diagram of a conventional phase margin detection circuit, and FIG. 7 is a diagram explaining the operation of the circuit in FIG. 6. . 3...Amplifier, 4...Automatic gain control circuit (AGC)
, 5... Subtraction circuit, 6... Filter circuit, 7...
Level detection circuit, 8...Peak detection circuit, 9...A
ND gate circuit, 10...attenuation circuit.

Claims (1)

[Claims] Regarding a read signal obtained by amplifying a signal read from a medium by a magnetic head to a predetermined level by an automatic gain control circuit, amplitude margin with respect to a threshold signal and phase discrimination margin with respect to a read clock. A read data merging guarantee circuit for testing a read data merge guarantee circuit includes: an attenuation circuit that generates an attenuation signal that attenuates the read signal by a value specified by an attenuation designation signal; a subtraction circuit that generates a subtraction signal; a filter circuit that generates a filter signal by removing frequency components below a predetermined frequency from the subtraction signal; and a filter circuit that compares the filter signal with the threshold signal and determines the level of the filter signal. is higher than the level of the threshold signal; a peak detection circuit that detects a maximum value of the filter signal and generates a peak signal when the maximum value is detected; The present invention is characterized in that it includes an AND circuit that performs an AND of a signal and the peak signal and outputs an AND signal, and a phase discrimination circuit that detects a phase margin of the AND signal with respect to the read clock. Read data margin guarantee circuit.