JPH01314043A - 5/4 conversion circuit - Google Patents

Abstract

PURPOSE:To attain fault diagnosis to a 5/4 conversion circuit accurately and quickly by applying parity check so as to detect a data error due to 5/4 conversion. CONSTITUTION:A parity generating circuit PGT generates a parity of a value corresponding to a binary data for each common bit number arranged serially in one transmission line prior to the 5/4 conversion and generates a parity of a value corresponding to a binary data for each common bit number arranged in parallel in four transmission lines after the 5/4 conversion. Then the parity and a parity from the parity generating circuit PGT are compared to apply parity check. Since the 5/4 conversion section TR is monitored in this way, if the 5/4 conversion section TR is faulty, the fault is discriminated from a fault of other section and no fault diagnosis of the 5/4 conversion circuit receives any hindrance.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a 5/4 conversion circuit for a digital communication system, and particularly to a 5/4 conversion circuit that performs a parity check.

(Prior art) In digital communication systems, for example, M20
The signal speed within the synchronous multiplex converter is 8.192 Mbit/see, but the signal speed on the transmission path between stations is, for example, 6.312 Mbit/see in the quadratic group.
The next group has a rate of 1.544 Mbit/see, and it is necessary to synchronize their mutual phases.

Therefore, when a signal is sent from the transmission line between stations to the synchronous multiplex converter, 5/4 conversion is performed in the transmission line interface circuit.

FIG. 2 is a block diagram of a conventional 5/4 conversion circuit.

In the same figure, TR is a 5/4 conversion unit, I HWI to IH
W5 is the five highways forming each transmission path on the input side of the 5/4 converter TR, and 0HWI to 0HW4 are the 5/4 converter TR.
The four highways forming each transmission line on the output side converted by HWI
-I A parity check circuit that performs a parity check on the data of HW5, PG is a parity generation circuit that generates parity corresponding to the data of 1 way 0HWI to 0HW4 on the output side of the 5/4 converter TR and sends it to the subsequent stage. It is.

SRI to SR4 are shift registers, and highway lH
Data for each time slot of W5 is sequentially shifted.

SEL is the selector, highway I HWI - I H
Data in W4 or data in shift registers 5RI-3R4 are selected and output to highways 0HWI to 0HW4.

Next, the conversion operation of the 5/4 converter TR will be explained with reference to FIG. Note that this figure is an explanatory diagram of the operation of the circuit in FIG. 1, and in the same figure, the portion excluding the parity generation circuit PGT and the parity check circuit PCT corresponds to the 5/4 converter TR in FIG. There is.

Each time slot of Highway I HW1 to I HW5 is numbered 1-1 to Blank, -5-1 to B11nk.
As shown in , there is one vacant time slot old ank every 5 time slots, and each time slot is
It consists of 8-bit data indicated by bit numbers .about.8. The selector SEL outputs the data of time slots No. 1 to No. 4 in the same figure regarding highways HWI to IHW4 to highways 0HWl to 0HW4, and in the meantime outputs the data of each time slot stored in each shift register 5RI to 8R4. The data of the 5th timeslot old ank
It is output to highway 0I (Wl to 0HW4) at the timing of . This operation is repeated to perform 5/4 conversion.

In the conventional monitoring system, the parity check circuit PC checks the data input to the 5/4 converter TR by comparing it with the parity sent from the previous stage.
The parity generation circuit PG generates parity for the data output from the 5/4 conversion section TR, and similarly checks it at a subsequent stage.

(Problem to be Solved by the Invention) However, in the above monitoring method, the 5/4 converter is not monitored, so if there is a failure in the 5/4 converter, it can be determined that it is a failure in other parts. This caused problems in fault diagnosis.

SUMMARY OF THE INVENTION In view of the above problems, it is an object of the present invention to provide a 5/4 conversion circuit that monitors the operation of a 5/4 conversion section.

(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention receives data on five transmission lines transmitted with one empty time slot interposed every five time slots, and The data of each time slot of the other transmission line is distributed to each free time slot of the four transmission lines, and 5/4 conversion is performed.
In the 4-conversion circuit, data of a common bit number is extracted from the data of each time slot of the other one transmission line according to the progress of the transmission bit, and is made to correspond to binary data for each common bit number. A parity generation circuit that generates parity generates parity corresponding to binary data for each common bit number according to the progress of transmission bits for data on the four transmission paths of the allocated time slot, and and a parity check circuit that performs a parity check by comparing the parity with the parity generated by the parity generation circuit.

(Function) According to the present invention, before 5/4 conversion, the parity generation circuit generates parity values corresponding to binary data for each common bit number arranged in series on one transmission path. After the 5/4 conversion, the parity check circuit generates a parity value corresponding to the binary data for each common bit number arranged in parallel on the four transmission lines,
A parity check is performed by comparing the parity with the parity generated by the parity generation circuit.

(Embodiment) Fig. 1 is a block diagram of a 5/4 conversion circuit showing an embodiment of the present invention, Fig. 3 is a detailed diagram of the parity check section of the circuit of Fig. 1, and Fig. 4 is a block diagram of a 5/4 conversion circuit showing an embodiment of the present invention. FIG. 5 is a timing chart showing the operation of the circuit shown in FIG. 3.

In FIG. 1, the same parts as in FIG. 2 are designated by the same reference numerals.

PGT is a parity generation circuit that generates parity for monitoring the 5/4 converter TR, EXI is an exclusive OR gate, and SRT is a shift register.

The shift register SRT is composed of D-type flip-flops Fl-F8 and AND gates ANDI-AND8, the number of which is the same as the number of bits of each time slot.

Exclusive or gate EXI has one highway 1 on the input side.
The serial data of HW5 and the output of the last-stage flip-flop Fl of the shift register SRT are received and output to the first-stage flip-flop FB of the shift register SRT via the antogenide AND8. Each time the data bit advances, the data is sequentially shifted to each of the next-stage flip-flops F7-Fl via the AND gates AND7-ANDI, and parity is output from the final-stage flip-flop Fl. R is a reset signal that causes flip-flop Fl-FB to be reset at the end of an empty time slot. 8MCLK is 8.192M bits/see, and IHWl to IHW5 (or 0HWI to 0HW4
) is performed in accordance with the progression of the bits.

The parity sequentially output from the flip-flop Fl is the same data of each bit 1 to 8 for the binary data of the first time slot 5-1 after reset, and
For data after -2, if the binary data of each bit is the same as the data of the previous time slot, it will be '0', and if it is different, it will be '1'. Therefore, the number of '1's for each bit is an odd number. When it becomes an even number, it becomes "1", and when it becomes an even number, it becomes '0'.

PCT is a parity check circuit that monitors the 5/4 converter TR, and is composed of exclusive OR gates EX2 to EX5 and an AND gate AND9. Each highway 0HWI on the output side
When the number of "1"s in the data of 0HW4 is odd for each bit, the exclusive OR gate EX4 outputs "1", and when it is even, it outputs "0". Exclusive OR gate EX5 compares the parity output from flip-flop F1 and the parity output from exclusive OR gate EX4, and outputs a parity alarm when they are different.

AND9 is an AND gate for masking, which receives the mask signal MSK in the 5-volume time slot shown in FIG.
Exclusive or game for the data of the relevant time slot)
The output of EX4 is enabled, the others are disabled, and a parity alarm is output for the time slot.

In addition, the shift register 5 in the timing chart of FIG.
In the output of RT (Fl), L indicates a low level,
1' to 8' are the data of the exclusive OR of each bit of data 5-1 and data 5-2, and 1#
~8'' is the exclusive OR data of data 1''~8゛ and data 5-3, P-1~P-8 is the exclusive OR of data 11~8# and data 5-4 This is the data.

In the circuit of FIG. 3, for example, the data of bit number 8 in each time slot 5-1 to 5-4 of the highway IHW 5 are "1" and "1", respectively.

0° and "1", the data in the shift register 5RT (Fl) in FIG. 5 is 8.8-.

8', P-8 are 6 "1", "O", "0" respectively
”.

becomes “1”, and on the other hand, highway 0HWI −0HW4
The data of the rightmost bit number 8 in FIG. 4 is '1
” is an odd number, exclusive or gate EX4
The data of the corresponding bit number becomes "1". When the mask signal MSK is at high level, the exclusive OR gate EX5
The data P-8 is compared with the data of the exclusive OR gate EX4. If they match, it is normal, but if they do not match, it is assumed that there is a data error, and a parity alarm is output from the AND gate AND9.

(Effects of the Invention) As explained above, according to the present invention, parity corresponding to binary data for each common bit number is generated for data on one transmission line on the input side of a 5/4 conversion circuit. For the transmission line on the output side, parity is also generated corresponding to the data distributed from the one transmission line, and the parity is checked by comparing both parities.
Data errors caused by 4-conversion are detected, and the 5/4 conversion circuit can be accurately and quickly diagnosed.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a 5/4 conversion circuit showing an embodiment of the present invention, Figure 2 is a block diagram of a conventional 5/4 conversion circuit, and Figure 3 is details of the parity check section of the circuit in Figure 1. 4 is an explanatory diagram of the operation of the circuit of FIG. 1, and FIG. 5 is a timing chart showing the operation of the circuit of FIG. 3. TR...5/4 conversion unit PGT...Parity generation circuit PCT...Parity check circuit l HWI-I HW5...Highway 0 on the input side
HWI~0HW4... Output side highway patent applicant Oki Electric Industry Co., Ltd. Nippon Telegraph and Telephone Corporation Agent Patent attorney Yoshi 1) Takashi Sei

Claims (1)

[Claims] Data on five transmission lines transmitted with one empty time slot interposed every five time slots is received, and data on the other one is transmitted in each empty time slot of four of the transmission lines. By allocating the data of each time slot of the main transmission path, 5/
In a 5/4 conversion circuit that performs 4 conversion, data of a common bit number is extracted from the data of each time slot of the other one transmission line according to the progress of the transmission bit, and a binary value is obtained for each common bit number. a parity generation circuit that generates parity corresponding to data; and a parity generation circuit that generates parity corresponding to binary data for each common bit number according to the progress of transmission bits for data on the four transmission paths of the allocated time slots. A 5/4 conversion circuit comprising: a parity check circuit that generates parity and compares the parity with the parity generated by the parity generation circuit to perform a parity check.