JPH03214949A - Signal path verification system for digital cross connector - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a signal path verification method for a digital cross-connect device for verifying signal paths in a digital cross-connect device, and enables accurate and high-speed signal path verification. Furthermore, with the aim of reducing the burden placed on processors in devices such as microcomputers, the system includes a reception interface unit that receives transmission line signals and converts them into VT signals in a virtual group frame format. a switch section that cross-connects VT signals from the receiving interface section; In a digital cross-connect device including a transmission interface section that converts a VT signal from a switch section into a transmission line signal and outputs the signal. At the reception interface section, signal path verification information is inserted into the undefined VT path overhead section of the VT signal, and at the transmission side interface section. By detecting this signal path verification information.
The signal path is configured to be verified.

[Field of Industrial Application] The present invention relates to a signal path verification method for a digital cross-connect device for verifying a signal path in a digital cross-connect device.

Digital cross-connect equipment. Generally, it is a device that arbitrarily cross-connects signals of several hundred channels to several thousand channels or more at the DS1 signal level. In this digital cross-connect device, it is necessary to confirm whether the cross-connect control information and the actual cross-connect status match for device maintenance. This verification needs to be able to be performed accurately and quickly.

[Prior Art] FIG. 7 shows ASYNC-DS3, DS2, DSIC.
A schematic configuration of a conventional digital cross-connect device that terminates various transmission line signals such as DS1 is shown. In FIG. 7, 51 is a receiving interface section that receives a transmission line signal and converts it into an internal frame, and 52 is a switch section that cross-connects the output signal from the receiving interface 5l. Reference numeral 53 denotes a transmission interface section that converts the signal after cross-connection in the switch section 52 into a transmission line signal and transmits the signal. 5
4 is a cross-connect control section that controls the switch section 52. This digital cross-connect device. As a frame structure for internal signal processing. A frame format as shown in Figure 8 is used. In the figure, φl is a time slot indicating input #l of the DSL signal, and FO and Fl are frame synchronization signals. Ci indicates a stuffing control signal, and Vl indicates a stuffing time slot. With conventional digital cross-connect equipment like this.
The basic signal rate within the device is 1.576 Mbps, and in the case of the frame structure shown in Figure 8, the DS
I signal speed variation is 1.5413M1{z to 1.55
It is possible to cover up to 122MHz. The staff ratio is approximately 5/18.

Here, the conventional signal path verification method for checking the match between the cross-connect control information and the actual cross-connect status is as follows.
This is performed according to the procedure shown in FIG. 9 while using the stuffing time slot Vl in the FIG. 8 frame.

In other words. At the reception interface section 5l. Usually when the Vl bit is a stuff bit. This Vl bit is set to a value of "0" for all channels, and when a bus check (signal path verification) is to be performed for a certain channel, the check is executed by a command from the microcomputer in the cross-connect control unit 54. Only the V1 bit of the channel to be used is set to the "l" value, and the V1 bits of other channels are set to the "O" value.

These signals are cross-connected by the switch section 52 and input to the transmission interface section 53. The transmission interface 53 that receives this signal detects Vl in the input signal.
Monitor bits. These transmission interface sections 53
is notified of the cross-connect control information from the microcomputer in advance, and therefore, by comparing this cross-connect control information with the actual cross-connect state obtained from the Vl bit information in the received signal. Each transmission interface section 53 is . It is possible to verify whether the cross-connection processing in the switch section 52 has been performed normally. This verification result is. The microcomputer is notified from each transmission interface section 53.

[Problem to be solved by the invention] The above signal path verification is as follows. Since it is performed sequentially for each channel, that is, one channel at a time, for example, 20
For systems with more than 00 channels. The time required to perform path checks on all channels becomes considerably long. Staff bit especially used for pass checking
1 does not always exist. Since the bus check must wait until this stuffing bit v1 is generated, the path check time becomes even longer. Also, the microcomputer is used for path checking. “
1” and to receive notification of the verification result of the transmission interface unit 53.Access to the channel interface unit is required at least twice, and this access is repeated for all channels. This puts a considerable processing load on the microcomputer.Furthermore, the only information bit for checking in the path check is the 1-bit information set in the Vl bit.There is no error in this Vl bit. etc., it is not possible to perform an accurate check.Therefore, the reliability of the bus check is low.Therefore, an object of the present invention is to make it possible to perform signal path verification accurately and at high speed. The object is to reduce the burden placed on a processor in a device such as a microcomputer. [Means for solving the problem] Fig. 1 is a diagram explaining the principle of the present invention. Digital cross-connect according to the present invention How to verify the signal path of the device.
A reception interface unit 61 receives a transmission path signal and converts it into a VT signal having a virtual group frame format; a switch unit 62 cross-connects the VT signal from the reception interface unit 61; and a switch unit 62 that transmits the VT signal from the switch unit 62. In a digital cross-connect device, the digital cross-connect device is equipped with a transmission interface section 63 that converts the signal into a signal and outputs the signal. At the receiving interface section 61. Signal path verification information is inserted into the undefined VT path overhead part of the VT signal. At the sending side interface section 63. By detecting this signal path verification information. It is configured to verify the signal path. [Effect 1 In the present invention. As a frame format for internal signal processing of digital cross-connect equipment. S O N E
T (Synchronus Optical NE
The VT (virtual group) frame format defined in Workl is used. As a result, the digital cross-connect device according to the present invention includes ASYNC-DS3,
DS2, DSIC. Not only conventional transmission line signals such as DS1 etc. OC signals that meet SONET standards (e.g. OCI)
,OC3. STS-1, VTI. 5 etc.) can also be cross-connected. The VT frame format is . As shown in Figure 1. Vl, V2, V3. V4's four VT path overhead sections and . It consists of four data parts each consisting of a bytes. The number of bytes a in the data section is Vl. 5 signal, a=26, VT2 signal, a=35, VT3 signal, a=53, and VT6 signal, a=107. Also VT
The path overhead part is the Vl and V2 bytes are the contents (
usage) has already been defined, but the V3 and V4 bytes are still undefined. Therefore, in this invention. Signal route verification is performed using this undefined VT path overhead section. That is, at the receiving interface section 61. Insert signal path verification information into this undefined VT path overhead section 3 or V4 of each channel signal. A switch section 62 cross-connects these signals. In the transmission interface section 63. The content of the undefined VT path overhead part of the signal after cross-connect is monitored, and this content is compared with the cross-connect control information given in advance from the microcomputer, and based on this, the cross-connect processing in the switch unit 62 is performed. Verify the signal path to see if it was performed correctly. The VT path overhead section into which signal path verification information is inserted is as follows. Both V3 and V4 are available, but V
If an intra-device frame synchronization signal for achieving frame synchronization within the device is inserted into the 4 bytes, it is appropriate to use the V3 byte. This is because the V3 byte does not necessarily exist in every cycle, so if the V3 byte is used as a frame synchronization signal, the frame synchronization characteristics may deteriorate. This is because even if the V3 byte is used for signal route verification, it will not have a major effect on verification.

[Example] Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 shows a digital cross-connect device using a signal path verification method as an embodiment of the present invention.

In Fig. 2. 1 is a receiving interface circuit.
This receiving interface circuit has data input as a data input.
DSI signals including multiple channels are SONET-V
T.I. 5 signals are input. A plurality of such receiving interface circuits l are provided. This reception interface circuit l has a speed converter 11, V
3 insertion section 12, V47L, -mu insertion section l3, ID insertion section 14. It is configured to include a pulse generator 15 and the like.

The speed converter 11 is a circuit that converts the input transmission path signal into the VT format, which is a frame format for internal signal processing, while converting the speed. ■3 Insertion part l
Reference numeral 2 denotes a circuit that sequentially inserts a path check data string containing a bus ID code as signal route verification information given from the ID insertion circuit 14 into the v3 byte of the converted VT format. The V4 frame insertion unit 13 is a circuit that inserts a frame synchronization signal for VT frame synchronization within the device into the v4 byte in the VT format.

Further, the pulse generator 15 is a circuit that generates various timing clocks within the reception interface circuit i.

The VT signals from these receiving interface circuits 1 are input to the switch circuit 2, respectively. This switch circuit 2
has the function of cross-connecting the VT signals of each Chakenru. VT of each channel after cross-connection in switch circuit 2
The signal is input to the transmission interface circuit 3. A plurality of transmission interface circuits 3 are provided, each of which includes a V4 frame detection section 31 . V3 detection section 32, speed conversion section 33, pulse generation section 34, ID companion section 35, ID
It is configured to include a comparison section 36 and the like.

Here, the V4 frame detection unit 3l is a circuit for detecting a 4-byte VT frame synchronization signal in the received VT signal. The V3 detection unit 32 is a circuit that detects the v3 byte in the VT signal. The speed conversion section 33 is a circuit that formats and speed-converts the VT signal into a transmission line signal and outputs it, the pulse generation section 34 is a circuit that generates various timing clocks in the transmission interface 3, and the ID companion section 35 is a V3 detection section 32. The ID comparison unit 36 is a circuit that synchronizes the V3 byte path check data string in the detected VT signal with the check frame synchronization signal included in the data and extracts the bus ID code. This circuit compares the detected path ID code with the reference ID code given from the microcomputer and outputs the verification result ERROR. VTl. used within the device. The frame format of 5 is shown in Figure 3. In FIG. 3, Vl, V2. V
3, V4 (7) Each byte is a VT path overhead byte (or service byte). Also, I is the information part, and 0 is the overhead pit part I Ct fixed at "0"'.
, Cz is a stuffing control bit section + Sl + St is a stuffing bit section. R is a reserved bit part.

In this VT frame format, the usage of the V1 and V2 bytes has already been defined. Also. An internal frame synchronization signal with a fixed pattern of "11101 000" is inserted into the undefined v4 byte. Bus check data is inserted into the V3 byte. An example of this path check data is shown in Figure 4.
The frame structure has a data length of 32 bits. Among these, the number of bits for checking frame identification (C frame synchronization) is 18 bits. Channel ■D data is 14 bits.

This 32-bit data is divided into 4 bytes of 8 bits each. Each of these is sequentially inserted into 3 bytes.

The signal path verification operation by this embodiment device will be explained below with reference to the flowchart of FIG. When a DSI signal or a VT1.5 signal is received by the reception interface section l, this signal is converted into a V in VT format by the speed conversion section l1.
It is converted into a T signal. The microcomputer writes the ID code of each channel into the ID insertion section l4 (step S2). Start the pass check (Step S3)
.

First, the v3 insertion unit l2 inserts the bus check data string shown in Figure 4 into 3 bytes of the VT signal (step S4).
. Furthermore, V4 in the VT signal is inserted in the V4 frame insertion section l3.
Insert the internal VT frame synchronization signal into the byte. It is sent to switch circuit 2 to perform cross-connection. In the transmission interface circuit 3, v4 in the received VT signal
The frame synchronization of the received VT signal is achieved by detecting the VT frame synchronization signal inserted in the byte by the V4 frame detection unit 3l, and the V3 byte in the received signal after frame synchronization is further detected by the V3 detection unit 32. ．． 10 synchronization unit 35 synchronizes the path ID code included in these 3 bytes using the path identification frame. And detect it while giving an appropriate number of protection stages. This pass ID code is sent to ■D comparison section 36. The ID comparison section 36 has . A reference ID code obtained from the cross-connect control information from the microcomputer is written, and this reference ID code is compared with the ID code input from the ID synchronization section 35 (step S5). Verify the signal path accordingly. It depends on whether these ID codes match or not. It is determined whether there is an error in the cross-connect processing in the switch circuit 2 (step S6). The determination result is latched and output to the microcomputer (steps S7, S8).

This processing is performed separately for each channel by hardware. The microcomputer monitors the verification result data latched by the hardware by polling (
Step S9). In this example method. The microcomputer is. In the reception interface circuit 1, check data including channel ID data is sent to the ID insertion section 14 for each channel.
This is because it only needs to be written once. Even if the check is repeated many times. The number of accesses from the microcomputer to the reception interface circuit 1 is only once unless there is a failure such as a power cut to the unit. Also in the transmission interface circuit 3. Once the reference ID code is written in the ID comparison section 36. Unless there is a cross-connect change (change in signal path history) or a power failure. There is no need to write data next. The number of accesses to the transmission interface circuit 3 can also be one. Furthermore, path checking is performed independently by hardware in each transmission interface circuit 3. The microcomputer can capture signal path verification results simply by polling the judgment data latched by these hardware circuits. This significantly reduces the processing load (number of processing steps) on the microcomputer compared to conventional methods. Therefore, the processing time required for signal path verification can be significantly reduced. Also, in this example. % By using the v3 byte (8 bits) in the JT signal to transmit check data. This was because there was more room in the amount of information to be transmitted for bus checks. Check data on channel with frame synchronization signal■
It becomes possible to convert the data into D data format. When performing a bus check using such a channel TD code with a frame synchronization signal. Since the ID code can be detected by providing an appropriate protection stage while maintaining frame synchronization in the check section provided on the transmission interface circuit 3 side, it is possible to extremely reduce errors in this channel ID code, thereby ensuring accuracy. This makes it possible to perform accurate signal route verification.

Furthermore, when comparing the speed of transmitting channel ID data with a frame synchronization signal between the conventional method using stuff bits and the method of the present invention, it is found that In such a case, the period per “l” bit is 700 μs on average.
Therefore, when sending channel ID data with a frame synchronization signal whose total data length is about 32 bits. Although the frame period is about 22.4ms, in the method of the present invention,
Even with data in the same 32 bits, the frame period only needs to be about 2 ms.

In Figure 6. An example of the overall configuration of the channel interface circuit of the digital cross-connect device according to the present invention will be shown in more detail and concretely. This example is. It incorporates a receiving interface circuit and a transmitting interface circuit into one unit. Each block within the unit has the following functions. The LB control block 101 mainly has . Performs local loopback and self-check loopback. Also.
Controls output data. The DEC block 102 decodes the B8ZS code or AMI data inputted by Univola and converts it into NRZ data. The BPV detection block 103 monitors the uni-bolar data and detects and outputs patterns that do not match the bi-bolar code rules. The IN DOWN detection block 104 monitors the input data and input clock, and detects the absence of a pulse of 175±75 bits. AIS control block 105 switches the output data to memory block 10.6 when IN DOWN detection block 104 detects a human power failure. The memory block 106 performs phase synchronization and speed conversion of the R side input data with the DAX device internal clock.

The DPC block 107 monitors the phase of the R-side memory block 106 and performs stuff request control.

The stuff control block 108 performs stuff control based on the stuff request output from the DPC block.

MRCK generation block 109 creates a clock for reading data from memory block 106.

The S/P control block 110 stores the data read from the memory block 106 in an 8 format suitable for data processing in subsequent stages.
Convert to bit parallel data.

The ID generation block tti converts the bus ID input from the microcomputer into a path ID format.

(3) The 3 generation block 112 divides the check data generated by the ID generation block 11l into 8 bits and inserts them into the v3 byte.

The Vl, V2 generation block (] block 113 inserts the NDF, VT size, and 10-bit pointer into the V1.V2/”C byte. ■The 4 generation block 114 inserts a frame synchronization pattern into the v4 byte. ■5 Occurrence Block 115 inserts the results of calculations in the BIP-2 count block into the v5 byte.
, V4 byte and v5 byte, R bit. Extra bits such as 0 bits, service bits, etc. are inserted and masked to create VT formatted data.

The B T P-2 counter R block l17 receives the Vl. in the VT data. Parity count is performed on data excluding V2, V3, and V4 bytes.

The P/S conversion block 118 converts parallel data for internal processing blocks into serial data.

The SELF control block 119 performs loopback during self-check. The PGR block 120 creates each l pulse used by the receiving side VT format conversion block.

The V4 detection block 121 detects a frame synchronization pattern inserted into 4 bytes from the data after passing through the switch.

A synchronization protection block 122 performs synchronization protection.

Since the S/P conversion block 123 performs internal processing in 8-bit parallel, it converts input serial data into 8-bit parallel data.

The PGS block 124 creates various pulses used in the VT format conversion block on the transmitting side. The Vl, V2 drop block 125 detects and outputs the Vl, V2 bytes from the input data on the transmitting side.

The pointer detection block 126 is one of the Vl and V2 bytes.
Detects 0 bit pointer. Performs staff control, etc. V3 drop block 127 detects ■3 bytes. Perform output. The ID detection block 128 receives the bus check data inserted in the V3 byte, synchronizes, and outputs the bus ID. The ID comparison block 129 is detected by the ID detection block l28. The output path ID is compared with the reference bus ID written by the microcomputer to determine an error. B I P-2 count S block/block 130 is Vl. V
2. Performs parity count of VT data excluding V3 and V4.

BIT staff control block 131G. Monitor the CI and C2 bits in the tVT data. The St and S2 bits are controlled by majority decision on the 3 bits.

OHBl'OpppcJ') 132 is Vl, V2, V
3. Detect overhead bytes such as ■5 bytes from VT data excluding V4. Output.

V5 (B I P-2) drop block 133 is 0
}BIP-2 data is detected from the V5 byte output by the IB drop block 132. Output. The BIP-2 comparison block 134 compares V5 (BIP-2
) The BIP-2 data outputted by the drop block 133 and the result calculated by the BIP-2 count S block 130 are compared and determined. MWCK generation block 135
creates a clock for writing DSI data into the S-side memory block 137.

The MPG S block 136 stores the V5 byte first, and the S side memory block 137 stores the vtx. s rate data D
Convert speed to SI rate.

The DPLL block 138 monitors write and read timing in the S-side memory block 137. A clock is generated digitally so that the phases do not cross each other. DSI data selection block 139 selects DSI output data.

The COD block 140 converts NRZ data into univollar data (AMI and B8ZS codes can be selected by setting). The microcomputer interface block 141 interfaces with the microcomputer. Perform various settings and monitor. The TIM DIV block 0-/block 141 creates timers for detecting various alarms inside the LSI.

[Effect of the invention] As explained above. According to the invention. It will be possible to check and verify signal paths within digital cross-connect devices quickly and reliably. Also. It is possible to immediately respond to expansion of the device without significantly increasing the processing load on the processor in the device, such as a microcomputer.Furthermore, since the present invention uses the VT format as the frame format for signal processing in the device, , conventional ASYNC-DS3. DS2, DSIC. Not only can it terminate transmission line signals such as DS1, but it can also terminate VTl. It becomes possible to terminate signals such as 5 signals.

[Brief explanation of drawings]

FIG. 1 is a diagram explaining the principle of the present invention. FIG. 2 is a block diagram showing a digital cross-connect device using a signal path verification method as an embodiment of the present invention. FIG. Diagram showing the SONET-VT frame format. FIG. 4 is a diagram showing the frame format of bus check data used in the embodiment device. Fig. 5 is a flowchart showing the processing procedure for signal path verification in the embodiment device, and Fig. 6 is a block diagram showing the overall configuration of the channel interface circuit in more detail. Figure 7 is a flowchart showing the schematic configuration of the digital cross-connect device. Figure 8 is a diagram showing a frame format used for signal processing in a conventional digital cross-connect device. and. FIG. 9 is a flowchart showing the processing procedure of conventional signal path verification. In the figure, l...Reception interface circuit 2...Switch circuit 3...Transmission interface circuit 11.33-...Speed conversion section l2...■3 insertion section 13...■4 Frame insertion section l4 ...ID insertion section 15.34...Pulse generation section 3l...V4 frame detection section 32...V3 detection section 35...ID synchronization section 36...ID comparison section 7 Is it power on the moon? Ichitenko Ichimeken Ichizuki Figure 1
Diagram MSB LSB 3rd diagram MSB LSB 3rd diagram Jigawa Hai E/l Signal class word Chichisho 9 processing hand 11 Ryo 5th Diagram name Original Digi/71 recross connect diagram 7

Claims (1)

[Claims] A receiving interface unit (61) that receives a transmission line signal and converts it into a virtual group signal (VT) having a virtual group frame format;
a transmission interface section (63) that converts the virtual group signal (VT) from the switch section (62) into a transmission line signal and outputs the signal.
), the receiving interface unit (61) receives a virtual group signal (VT
), signal route verification information is inserted into an undefined path overhead section in A signal path verification method for a digital cross-connect device.