JPH01316905A - Hybrid integrated circuit board - Google Patents
Hybrid integrated circuit boardInfo
- Publication number
- JPH01316905A JPH01316905A JP63146785A JP14678588A JPH01316905A JP H01316905 A JPH01316905 A JP H01316905A JP 63146785 A JP63146785 A JP 63146785A JP 14678588 A JP14678588 A JP 14678588A JP H01316905 A JPH01316905 A JP H01316905A
- Authority
- JP
- Japan
- Prior art keywords
- resistance value
- resistor
- conductor
- conductors
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004020 conductor Substances 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract description 4
- 229910052709 silver Inorganic materials 0.000 abstract description 4
- 239000004332 silver Substances 0.000 abstract description 4
- 238000012858 packaging process Methods 0.000 abstract 1
- 238000009966 trimming Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 7
- 230000006866 deterioration Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000000470 constituent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Landscapes
- Apparatuses And Processes For Manufacturing Resistors (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野1 本発明は混成集積回路基板に関するものである。[Detailed description of the invention] [Industrial application field 1 The present invention relates to hybrid integrated circuit boards.
[従来の技術1
従来、等しい回路内容を持ち、且つ、要求される抵抗値
が異なる複数種の混成集積回路を開発する場合、導体及
び抵抗体形成工程の準備時間低減、並びに印刷スクリー
ンあるいは露光マスクの管理点数削減を図る上で、品種
ごとに個別の導体パターン及び低抗体パターンを用意せ
ずに、導体パターン及び抵抗体パターンを共用すること
が理想とされている。[Prior art 1] Conventionally, when developing multiple types of hybrid integrated circuits that have the same circuit content but different required resistance values, it has been necessary to reduce the preparation time for the conductor and resistor forming process, and to use a printing screen or exposure mask. In order to reduce the number of points to be managed, it is ideal to share conductor patterns and resistor patterns without preparing individual conductor patterns and low-antibody patterns for each product type.
しかしながら、同−面積抵抗値を持つ材料で抵抗体を形
成することを条件として、パターンを共用した場合、高
い目標抵抗値を要求される品種については、抵抗体のト
リミング桟幅が短かくなり、抵抗値精度の悪化、許容電
力量の低下等の不都合が生じる。However, if the patterns are shared on the condition that the resistors are made of materials with the same area resistance value, the trimming width of the resistor will be shortened for products that require a high target resistance value. This causes disadvantages such as deterioration of resistance value accuracy and reduction of allowable power amount.
第1図(a)は、パターンを共用した混成集積回路基板
の一例を説明するための部分回路図で、第1図(b)及
び(c)は第1図(a)の回路図に対応するパターン図
である6導体1と導体3の間に抵抗体2が形成され、導
体3はトランジスタ5の電極4に接続された構成になっ
ており、回路は抵抗体2にトリミング切込み満6を入れ
て調整する。Figure 1(a) is a partial circuit diagram for explaining an example of a hybrid integrated circuit board that shares a pattern, and Figures 1(b) and (c) correspond to the circuit diagram in Figure 1(a). The resistor 2 is formed between the conductor 1 and the conductor 3, and the conductor 3 is connected to the electrode 4 of the transistor 5. Insert and adjust.
第1図(b)は、低い目標抵抗値を要求される品種にお
けるトリミング後の状態を示したものであり、抵抗体2
のトリミング桟幅は正常である。Figure 1(b) shows the state after trimming in a product that requires a low target resistance value.
The trimming bar width is normal.
第1図(c)は、高い目標抵抗値を要求される品種にお
けるトリミング後の状態を示したものであり、抵抗体2
のトリミング桟幅は短か過ぎる。Figure 1(c) shows the state after trimming in a product that requires a high target resistance value.
The width of the trimming bar is too short.
なお、第1図(b)及び(C)にそれぞれ示される抵抗
体2は同一面積抵抗値を持つ材料で形成されたものであ
る。The resistors 2 shown in FIGS. 1(b) and 1(C) are made of materials having the same sheet resistance value.
〔本発明が解決しようとする問題点]
上記の構成の混成集積回路基板において、パターンを共
用する品種の中で、高い目標抵抗値を要求される品種に
ついては、抵抗体のトリミング桟幅が短かくなり過ぎ、
抵抗値精度の悪化、許容電力量の低下等の問題が生じる
。[Problems to be Solved by the Invention] In the hybrid integrated circuit board having the above configuration, among the types that share the pattern, for the types that require a high target resistance value, the trimming width of the resistor is short. It's getting too much,
Problems such as deterioration of resistance value accuracy and decrease in allowable power amount arise.
〔問題を解決するための手段1
本発明は、基板に導体及び抵抗体を有する混成集積回路
基板において、直列接続された抵抗体上に抵抗体短絡用
導体を設け、不用となる抵抗体部分の両端をチップジャ
ンパーあるいは銀ペースト等で短絡することにより、上
記の問題点を解決しようとするものである6
[実施例〕
次に、本発明の実施例について図面を用いて説明する。[Means for Solving the Problem 1] The present invention provides a hybrid integrated circuit board having a conductor and a resistor on the substrate, by providing a conductor for shorting the resistor on the resistors connected in series, and removing unnecessary portions of the resistor. This is an attempt to solve the above problem by short-circuiting both ends with a chip jumper, silver paste, etc.6 [Example] Next, an example of the present invention will be described with reference to the drawings.
第2図は本発明の一実施例を説明するためのパターン図
で、第1図と同一機能を有する箇所については同一符号
を付している。FIG. 2 is a pattern diagram for explaining one embodiment of the present invention, and parts having the same functions as those in FIG. 1 are given the same reference numerals.
第2図の特徴は、第1図(b)及び(C)に示すような
異なる抵抗値を要求する複数種の混成集積回路基板にお
いて、パターンを共用でき、且つ、構成する抵抗体のト
リミング加工において正常なトリミング桟幅を残した抵
抗値調整ができるところにある。The feature of Fig. 2 is that the pattern can be shared among multiple types of hybrid integrated circuit boards that require different resistance values as shown in Fig. 1 (b) and (C), and the trimming process of the constituent resistors The resistance value can be adjusted while leaving the normal width of the trimming bar.
それは、抵抗体2を適当な抵抗値比率に分割する抵抗体
短絡用導体7を用意することによって実現できる。This can be realized by preparing a resistor shorting conductor 7 that divides the resistor 2 into appropriate resistance value ratios.
第2図で第1図(b)のトリミングされた抵抗体2に相
当する低い目標抵抗値を得る場合は、導体3と抵抗体短
絡用導体7の間で抵抗値調整を行ない、部品実装工程時
に導体1と抵抗体短絡用導体7の間をチップジャンパー
あるいは銀ペースト8で短絡する。In order to obtain a low target resistance value in FIG. 2 corresponding to the trimmed resistor 2 in FIG. 1(b), the resistance value is adjusted between the conductor 3 and the resistor shorting conductor 7, and At times, a chip jumper or silver paste 8 is used to short-circuit the conductor 1 and the resistor short-circuiting conductor 7.
また、第2図で第1図(C)のトリミングされた抵抗体
2に相当する高い目標抵抗値を得る場合は、導体1と導
体3の間で抵抗値調整な行ない、導体1と抵抗体短絡用
導体70間は開放しておく。In addition, if you want to obtain a high target resistance value in Figure 2 that corresponds to the trimmed resistor 2 in Figure 1 (C), adjust the resistance value between conductor 1 and conductor 3, The short circuit conductors 70 are left open.
以上説明したように、本発明によれば、等しい回路内容
を持ち、且つ、要求される抵抗値が異なる複数種の混成
集積回路基板を開発するにあたって、品種にかかわらず
、要求される抵抗値精度、許容電力量を容易に得ること
ができる。As explained above, according to the present invention, when developing multiple types of hybrid integrated circuit boards having the same circuit content and different required resistance values, the required resistance value accuracy can be achieved regardless of the product type. , the allowable amount of power can be easily obtained.
また、同時に、導体及び抵抗体形成時の準備時間低減、
並びに印刷スクリーンあるいは露光マスクの管理点数削
減が実現され大幅な製造原価の低減を図ることが出来る
。At the same time, it also reduces preparation time when forming conductors and resistors.
In addition, the number of printing screens or exposure masks to be managed can be reduced, leading to a significant reduction in manufacturing costs.
第1図はパターンを共用した従来の混成集積回路の一例
を説明するためのものであって、(a)は部分回路図、
(b)及び(c)は(a)の回路図に対応するパターン
図である。
第2図は本発明の一実施例のパターン図である。
図中1は導体、2は低抗体、3は導体、4はトランジス
タの電極、5はトランジスタ、6はトリミングの切込み
溝、7は抵抗体短絡用導体、8はチップジャンパーある
いは銀ペーストをそれぞれ示す。FIG. 1 is for explaining an example of a conventional hybrid integrated circuit that shares a pattern, and (a) is a partial circuit diagram;
(b) and (c) are pattern diagrams corresponding to the circuit diagram of (a). FIG. 2 is a pattern diagram of one embodiment of the present invention. In the figure, 1 is a conductor, 2 is a low antibody, 3 is a conductor, 4 is a transistor electrode, 5 is a transistor, 6 is a trimming groove, 7 is a resistor shorting conductor, and 8 is a chip jumper or silver paste. .
Claims (1)
、導体間に直列に接続された抵抗体上に、抵抗体短絡用
導体を設けたことを特徴とする混成集積回路基板。1. A hybrid integrated circuit board having a conductor and a resistor on a substrate, characterized in that a resistor shorting conductor is provided on the resistor connected in series between the conductors.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63146785A JPH01316905A (en) | 1988-06-16 | 1988-06-16 | Hybrid integrated circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63146785A JPH01316905A (en) | 1988-06-16 | 1988-06-16 | Hybrid integrated circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01316905A true JPH01316905A (en) | 1989-12-21 |
Family
ID=15415484
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63146785A Pending JPH01316905A (en) | 1988-06-16 | 1988-06-16 | Hybrid integrated circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01316905A (en) |
-
1988
- 1988-06-16 JP JP63146785A patent/JPH01316905A/en active Pending
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