JPH01320531A - Display device - Google Patents

Abstract

PURPOSE:To perform the attachment of a priority order for making a window into a multiwindow by providing two pairs of display control systems, and controlling the priority order of display of the window. CONSTITUTION:The element of the two pairs of display control systems having the same function performs the same operation independently. In the control system on one side, a multiwindow generation/control circuit 1 suppresses the generation of the multiwindow and that of the readout address of a frame buffer 2. And the buffer 2 selects and inputs the address having the highest priority, and reads out image data according to the readout address. The image data is inputted to a shift register 3, and is converted to parallel-serial data. In the control system on the other side, the data is converted to parallel-serial data by a shift register 7 via the same process. Here, a CPU transfers display sequence, and stores it in a priority register 9, and controls the priority order by a priority order control circuit 10, and opens the tri-state gate 4 or 8 of the register 3 or 7 having the higher priority order. Thereby, it is possible to realize the making of the window into the multiwindow on which the priority order is attached.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a display device having a multi-window control device for displaying a plurality of windows in an arbitrary priority order and at high speed in a graphic display or a character display. .

[Summary of the invention]

The present invention provides a multi-window generation/control circuit that controls the generation of multi-windows and a frame buffer read address, and a frame that reads image data stored internally according to the read address generated from the multi-window generation control circuit. It has two display control systems consisting of a buffer, a shift register that exchanges the image data output from the frame buffer in parallel/serial, and a tristate gate that controls the output/non-output of the image data output from the shift register. , two sets of multi-windows each consisting of a plurality of windows are generated from each display control system.

Furthermore, it is comprised of a priority register that stores the display priorities of the two sets of multi-windows, and a window priority control circuit that controls the priorities of the two sets of multi-windows according to the display priorities sent from the priority registers. , which enables faster display of more windows.

[Prior Art] Conventionally, when realizing multi-window display, it was often realized by software, and there were many methods of reading out a window image created on a frame buffer and displaying it on a CRT. In addition, when implementing this with hardware, a limited number of multi-windows are implemented using large-scale hardware.

[Problem to be solved by the invention]

In conventional technology, when implemented in software, the contents of the frame buffer must be rewritten every time the window priority is changed, which imposes a heavy software load.In order to prevent image distortion during the rewriting period,
Special techniques such as the tuple buffer method had to be used. Furthermore, when implementing this using hardware, the number of windows that can be displayed is limited due to hardware scale and timing constraints.

[Means to solve the problem]

In order to solve the conventional problems, the present invention includes a first multi-window generation/control circuit, a first frame buffer, a first shift register, and a second multi-window generation/control circuit.
Out of the two sets of multi-windows generated in the two sets of display control systems consisting of a control circuit, a second frame buffer, and a second shift register, which multi-window data is sent to the first tri-state gate or the second tri-state gate? The configuration is such that a prioritized multi-window is displayed on the CRT by controlling input from the state gate to the LtJTDAC using a priority register and a window priority control circuit.

[Effect]

The multi-window generation/control circuit inputs an image data read address to the first frame buffer in synchronization with the display cycle of the CRT. The first read address is the address of the storage area of the window with the highest priority among the multiple windows overlapping the current display position.
selected in the multi-window generation/control circuit of
input into the frame buffer of

The first frame buffer reads the image data according to the read address sent from the first multi-window generation/control circuit, and inputs it to the first shift register.

The first shift register converts image data input in parallel from the first frame buffer into serial data and inputs the serial data to the first tristate gate.

Each element of the second multi-window generation/control circuit, the second frame buffer, and the second shift register is different from each element of the first multi-window generation/control circuit, the first frame buffer, and the first shift register. works the same way.

The priority register is transferred from the CPU and stores the display priorities of two sets of multi-windows generated by the first and second multi-window generation/control circuits. Furthermore, the stored display priorities are input to the window priority control circuit.

The window priority control circuit selects a first one from the display code of each window input from the first and second multi-window generation/control circuits and two sets of multi-window display priorities input from the priority register. and the second 1--Rice Chi 1--gate.

Through the operations of the above elements, the two sets of prioritized multi-windows are further prioritized to 111th priority and are converted into multi-windows.

〔Example〕

An actual hh example of the present invention will be explained below with reference to the drawings.

In FIG. 1, a multi-window generation/control circuit A generates/controls two windows A1 and Ay as shown in FIG. In this embodiment, in order to simplify the explanation, the multi-window generation/control circuits A and B''! shown in FIG.
However, it goes without saying that a window further north than this is possible.

The multi-window generation/control circuit A1 generates an image data read address in synchronization with the display cycle of the screen and inputs it to the frame buffer A2 via the control line 14. The display priority l1Ii is generated from the multi-window via the 6iI line 13 of the CP I, J, and is input to the control circuit A1, and the hidden windows At and Al are displayed in priority order l1Ii. When displaying the overlapping portion of A2, it is used to determine which window's read address should be input to frame buffer A2.

Furthermore, in synchronization with the address input to the frame buffer A2, the multi-window generation/control circuit A1 assigns window priority to two flags, window flags A+a and A2□, which indicate which window is currently being displayed. It is input to the ranking control circuit via the control line t.

Figure 2 shows window flag A when horizontal scanning line A is scanned/displayed in the area where windows AT and A2 overlap.
+ , A 2 and the display priority of windows A and A2, which show the relationship between addresses A141, A, and b, and the screen, are the ivJ sound set as A, , A, and the addresses of the overlapped parts of 0. I/S has high priority window A.
, address A + b is input to the frame buffer A2, and address A2b is input to the window A2 only portion. Furthermore, as shown in FIG. 2, the line/domain flag Aha is "T(" during the period when 5 addresses AH are input to the frame buffer A2, and is "I," during other periods.
”, the window flag A2. is the address A2b.
“H” only during the period when is being input to frame buffer A2.
”, and other periods are “I,”.

The frame buffer A2 reads the image data stored therein according to the image data read address A1b or A2b input from the control line 14, and outputs it to the control line J5.

The means for writing image data into frame buffers A2 and B6 is the same as in the prior art and will not be described herein.

Shift register A3 converts parallel data inputted from control line 15 into serial data and outputs it to control line P.

By repeating the above process for all scanning lines on the screen, windows A, , A2 are generated.

The multi-window generation/control circuit B5 in FIG. 1 includes the multi-window generation/control circuit A1, the frame buffer B6, the frame buffer A2, and the shift register B7.
operates in the same way as shift register 83, and generates a window by repeating for all scanning lines in the same way as described in ijI. The windows generated by this process are called B, ,B, and by the process of zero or more, two sets of multi-windows are generated.

The priority register 9 in FIG. 1 stores two sets of multi-window display priorities inputted from the CPU through the control line 13 and outputs them to the control line 22. The two sets of multi-windows are generated by the series of processes described above.

The window r highest order control circuit 10 receives control lines 20 and 2 from the multi-window generation/control circuits A1 and B5.
Using the window flag input via 1 and the display priority input from the priority register 9 via the control line 22, determine which of the license state gates A4 and B8 to open. and control line 23.
A control signal is output to either one of 24. The tri-state gates A4 and B8 output one of the image data input from the control line 16 or 19 to the control line 25 in accordance with the signals on the control lines 23 and 24, even if there is no image data or no image data. The tristate gate is controlled to be open.

The LUTDAC (lookup table and DA converter) 11 converts the image data input from the control line 25, inputs it to the CRT 12 via the control line 26, and outputs the image data to the CRT 12 via the control line 26.
T12 displays an image. LUTDAC II and CRT
Processing No. 12 uses a conventional technique, and therefore will not be described in detail here.

By repeating the above process for all the scanning lines of the screen, the two sets of multi-windows are displayed on the screen according to the priority order.

Using FIG. 3, the window priority control circuit 10
The processing will be explained in relation to screen display.

In this case, the priority order of the 2Mi windows is:
A + > A 2 > B + > B 2. The lower timing in FIG. 3 is the window flag Al11 and Aim input from the control line 20 and the window flag Baa and 8
2m and each timing of the tristate gate control signal output to the control lines 23 and 24.

Window flag I A + □, A x a and Blm,
82m are flags in two independent sets of multi-windows, and on the horizontal scanning line H, At>A,
According to the display priority order of >B+>B2, as shown in FIG. 3, the window flag with the higher priority becomes "H'" in the overlapping portion. These two sets of window flags (
4), the overlapping position of the two sets of multi-windows is determined.

When two sets of windows overlap, the display priority 111
According to the position, the two tristate gates A4, B
A control signal for controlling which of the terminals 8 is opened is generated and output to control lines 23 and 24. In the case of FIG. 3, according to the priority order, the tristate gate W is at H" in the part where A or A2 and B1 or B2 overlap, and the control line 23 is in the H" state in the part where only A or A2 is present. , B.T.
Or, in the case of only B7, the control lines 24 are each "open". In this case, it is assumed that the tri-state gates Ad and Bh are opened when the control line 23 or 24 is "open".Image data The portion without is shown as the hatched portion in FIG. 3, and this portion is controlled so that any one of the gates is opened. When tristate gate B8 is opened, the hatched portion in FIG. 3 becomes Hl.

By repeating the above processing for all the scanning lines of the screen, the multi-window display of the present invention is realized. Fourth
The display priority in Figures and Figure 5 is A+ >A2 >B+
Display examples in the case of >B2 and B, >B2 >A, and >A2 are shown.

In this embodiment, two sets of window generation systems are controlled with priority jIR, but it goes without saying that it is possible to increase the number of window generation systems. Although the number of windows that can be processed within the window generation system is set to two in this embodiment, it is also possible to increase this number.

Further, in the window priority control circuit 10 of this embodiment,
Turn each of the two multi-window generation systems ON10F.
By having the function of F, it is possible to easily change the number of display windows.

〔Effect of the invention〕

As described above, the present invention can double or triple the effectiveness of multi-windows generated by hardware.

It also expands the concept of the original purpose of multi-windows, which is to present an environment that gives the impression that multiple displays are operating on one display.

Furthermore, if it is realized in software, it is possible to provide a much faster environment in comparison.

[Brief Description of the Drawings] Fig. 1 is an explanatory diagram of a display device using the present invention, Figs. 2 and 3 are timing explanatory diagrams showing the screen display and the timing of each signal in the embodiment of the present invention, FIGS. 4 and 5 are explanatory diagrams showing display examples of the present invention. 1... Multi-window generation/control circuit A2... Frame buffer A 3... Shift register A 4... Tri-state gate A 9... Priority register 10... Window generation priority control circuit Person Seiko Electronics Industries Co., Ltd. Representative Patent Attorney Takayuki Hayashi −−−−−−−−
11111”
q1 soto 7 fuu fu A? Figure 2 7.1 min ri″g fixed B kite 4〕 Figure 3

Claims (1)

[Claims] In a display device such as a graphic display or a character display, a) a multi-window generation/control circuit that controls multi-window generation control and frame buffer read address generation; a frame buffer that reads image data stored internally according to a read address generated from a window generation control circuit; c) a shift register that converts image data output from the frame buffer into parallel/serial; and d) the shift register. a display control system consisting of a tri-state gate that controls the output/non-output of output data from the register, and e) a multi-window generation control circuit, a frame buffer, a shift register, and a tri-state gate that has the same function as the display control system. Another display control system consisting of a gate; f) a priority register that stores the priority order of multi-windows displayed on the screen; and g) window priority control that controls the display priority of windows in multi-window display. The two sets of multi-windows individually generated by the two sets of display control systems are connected to one CRT based on the priority order.
A display device characterized by displaying on the top.