JPH01320543A - Microprocessor device - Google Patents

Abstract

PURPOSE:To prevent a signal value from being changed by attaching another digital circuit on an analog processor device, and holding an output signal without drifting for a long time when a fault is generated in the operation of the processor. CONSTITUTION:When the operation of a microprocessor 1 is performed normally, a digital signal following the output signal Vout of a signal holding circuit 2 at every constant cycle is held at a counter 4 by a loop consisting of a counter 4, a D/A converter 5, a comparator 6, and a logic circuit 7. When abnormality is generated in the operation of the processor 1 at such state, the fact is detected by a monitoring means 3, and a switch SW1 is operated, then, the processor 1 is separated. In other words, a gate control circuit 73 in the circuit 7 receives a signal from the means 3, and cancels the above loop, and simultaneously, turns on the switch SW1 until malfunction in a synchronous circuit 74 is eliminated. Next, when the fault is eliminated, the digital signal without having the fault just before held at the counter 4 is inputted to the signal holding circuit 2 via the converter 5, and the output signal Vout is sent out from the circuit.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention relates to a microprocessor device that includes a microprocessor that performs predetermined calculations and a signal holding circuit that holds signals from the microprocessor as analog signals. More specifically, the present invention relates to a microprocessor device that is capable of holding the output of a signal holding circuit immediately before the abnormal operation occurs without drift when the abnormal operation of the microprocessor occurs.

(Prior art) Conventional signal holding circuits that hold signals from microprocessors as analog signals use sample-and-hold circuits that use capacitors. The hold switch was turned off to allow the capacitor to hold the output signal just before the malfunction occurred.

(Problem to be Solved by the Invention) However, a device configured to hold a signal in a capacitor has a problem in that if this state is continued for a long time, the signal value changes slightly due to leakage current.

The present invention has been made in view of the above problems, and its purpose is to add a separate digital circuit to the conventional one, so that the output signal can be extended over a long period of time without drifting when the microprocessor malfunctions. The object of the present invention is to realize a microprocessor device that can keep time.

(Means for Solving the Problems) FIG. 1 is a block diagram showing the basic configuration of the present invention. In FIG. 3 is a monitoring means for monitoring the operation of the microprocessor 1, and SWl is a signal holding circuit for holding the signal holding circuit 2 and the microprocessor 1 as an analog signal. 4 is a counter; 5 is a D/A converter that converts the digital signal from the counter 4 into an analog signal; 6 is a signal from the D/A converter 5; A comparator SW2 for comparing the signal from the signal holding circuit 2 is a second switch means for applying the signal from the D/A converter 5 to the input side of the signal holding circuit 2.

7 inputs the clock, the signal from the monitoring means 3, and the signal from the comparator 6, and while the monitoring means 3 does not detect any abnormal operation of the microprocessor 1, the signal from the comparator 6 is input to the counter 4 until the signal from the comparator 6 is inverted. A clock is supplied so that the value of the counter follows the output of the signal holding circuit 2 at predetermined intervals, and when the monitoring means 3 detects an abnormal operation of the microprocessor 1, the following operation is stopped and the value of the counter 4 follows the output of the signal holding circuit 2. This is a logic circuit that holds the output of the second switch SW2 and drives the second switch SW2.

(Function) While the microprocessor 1 is operating normally, the signal from the microprocessor 1 is sent to the first switch means S.
The signal is output via W1 and the signal holding circuit 2. In this state, the count value of the counter 4 follows the output of the signal holding circuit 2 through a loop including the comparator 6 and the logic circuit 7.

When the microprocessor 1 malfunctions, the logic circuit 7 stops the tracking operation and transfers the count value held in the counter 4 to the second switch SW2 and the signal holding circuit 2.
Output via .

(Example) Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram showing an embodiment of the present invention. In this example, the controller is configured using a microprocessor.
In the microprocessor 1, 11 is an arithmetic control unit (CPU).
), 12 is a ROM that stores various programs and data.
, 13 is a RAM storing data, arithmetic expressions, etc., and 14 is an input/output board, which are connected to each other via a bus. Reference numeral 15 denotes a comparator, into which the measurement signal Pv from the process selected by the multiplexer 16 and the set value (target value) signal Sv are input to one input terminal. 16 is D that converts the calculation result from the microprocessor 1 into an analog signal.
An analog signal from the /A converter is applied to the signal holding circuit 2. Note that the output signal of the D/A converter 16 is applied to the other input terminal of the comparator 15, and when converting the measurement signal pv or set value (target value) signal SV into a digital signal, A /D conversion loop is formed.

In the signal holding circuit 2, SO is the microprocessor 1
20 is a hold capacitor, and 21 is an amplifier. Monitoring means 3 for monitoring the operation of the microprocessor 1
In this case, a watchdog timer is used, and when this timer expires, it is assumed that a malfunction has occurred in the microprocessor, and the FATL lamp is turned on and the FATL lamp is turned on.
It is configured to output the AIL signal to the logic circuit 7.

Logic episode F! @7 inputs the gates 71 and 72 that input the clock CLK, the Goo 1-control circuit 73 that controls these gates, the FAII from the monitoring means 3, Shinzuki, and the clock, and drives the second switch SW2. Synchronous circuit 7
It consists of 4.

Reference numeral 70 denotes a manual operation means having an increase switch INC5 and a decrease switch DEC, the output of which is applied to the gate control circuit 73. This manual operation means 70 is used when the microprocessor 1 is in a state where the moving ear is abnormal and the output signal Vout't is changed.

The operation of the apparatus configured in this way will be explained next.

FIG. 3 is a time chart I showing an example of the operation.

First, it is assumed that the microprocessor 1 is operating normally. In this state, the monitoring means 3 does not time up, and the first switch SWt is connected to the contact a (
It is connected to the IJJ (D/A converter 16@), and the results of control calculations such as proportional and integral operations by the microprocessor 1 are sent from the signal holding circuit 2 via the D/A converter 16 and the first switch SWI. As the analog signal Vout, (
It is output as shown in d).

The output signal Vout of the signal holding circuit 2 is also applied to one input terminal of the comparator 6, and the logic circuit 73 controls the clock CLK by opening the gate 71, for example, until the signal from the comparator 6 is inverted. , is applied to the tJP@ child of the counter 4. Counter 4 counts applied clocks,
The D/A converter 5 converts this into an analog signal Vd and applies it to the other input terminal of the comparator 6.

The count value of counter 4 increases as shown in (f), and D/
When the output Vd of the A converter 5 becomes equal to the output signal Vout from the signal holding circuit 2, the output of the comparator 6 is inverted as shown in <g).

The logic circuit 7 receives the inverted signal from the comparator 6, stops supplying the clock to the counter 4, and holds the count value of the counter 4 as shown in (f). This counter 4
The count value is reset at regular intervals T by the reset pulse shown in (e) obtained by dividing the clock shown in (b).

When the microprocessor 1 is operating normally, a loop formed by the counter 4, the D/A converter 5, the comparator 6, and the logic circuit 7 sends the output signal V of the signal holding circuit 2 to the counter 4 at regular intervals. .

The digital signal following ut is held.

In such a state, if an abnormality occurs in the movement of the microprocessor 1, the monitoring means 3 detects the deviation and outputs a FAIL signal as shown in a), and also turns the first switch SWI on (h). As shown in the figure, the contact is driven from the contact a side to the contact side (the output from the microprocessor 1 is disconnected).

When the gate control circuit 73 receives the FAIL signal from the monitoring means 3, the gate control circuit 73 outputs the output Vou of the signal holding circuit 2 to the counter 4.
When the digital signal corresponding to t is held, the loop formed by the counter 4, D/A converter 5, comparator 6, and logic circuit 7 is released. Further, upon receiving the FAIL signal from the monitoring means 3, the synchronization circuit 74 turns on the second switch SW2 as shown in (1) from the next cycle until the FAIL signal disappears.

When the second switch SW2 is turned on, the digital signal held in the counter 4 (this digital value corresponds to the output Vout of the signal holding circuit 2 immediately before the first switch SW1 is driven) is transferred to the D/A The signal is converted into an analog signal via the converter 5 and applied to the input side of the signal holding circuit 2.

Therefore, the output signal V from the signal holding circuit 2 in this state
Since ou t is held digitally by the counter 4, it will not drift over a long period of time.

In such a state, the switch I of the manual operation means 70
When NC or DEC is operated, the gate control circuit 73 receives this and outputs the clock to the UP terminal of the counter 4 or
Apply to DNnA child. Therefore, the value of the output signal V out from the signal holding circuit 2 can be changed manually.

In the above embodiment, the comparator 6 is configured to input the output voltage of the amplifier 21 of the signal holding circuit 2, but it may also be configured to input the voltage of the hold capacitor 20.

Further, although the output Vd obtained by D/A converting the digital signal of the counter 4 is applied to the input side of the signal holding circuit 2 via the second switch and the first switch sw1, the second switch SW2 is Alternatively, the signal may be directly applied to the input side of the signal holding circuit 2 via the signal holding circuit 2.

(Effects of the Invention) As described above in detail, according to the present invention, the microprocessor is capable of holding the output signal of the signal holding circuit for a long time without drifting when the microprocessor malfunctions. The device can be realized.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing the basic configuration of the present invention, Figure 2 is a block diagram showing the basic configuration of the present invention.
The figure is a block diagram showing an embodiment of the present invention, and FIG. 3 is a time church showing an example of its operation. 1...Microprocessor 2...Signal holding circuit 3...Monitoring means 4...Counter 5...D/A converter 6...Comparator 7...Logic circuit SWI...No. 1 switch SW2...Second switch Figure 1'%53 Figure

Claims (1)

[Scope of Claims] A microprocessor that performs predetermined calculations; a signal holding circuit that holds signals from the microprocessor as analog signals; monitoring means that monitors the operation of the microprocessor; a first switch means for disconnecting the signal holding circuit and the microprocessor when an abnormal operation is detected; a counter; and a D/A converter for converting the digital signal from the counter into an analog signal. a comparator that compares the signal from the D/A converter with the signal from the signal holding circuit; and a second switch that applies the signal from the D/A converter to the input side of the signal holding circuit. input means, a clock, a signal from the monitoring means, and a signal from the comparator, and as long as the monitoring means does not detect an abnormal operation of the microprocessor, the clock is applied to the counter until the signal from the comparator is inverted. The value of the given counter is made to follow the output of the signal holding circuit at predetermined intervals, and when the monitoring means detects an abnormal operation of the microprocessor, the following operation is stopped and the counter is made to hold the output of the signal holding circuit. and a logic circuit for driving a second switch.