JPH0621992B2 - Microprocessor device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor device including a microprocessor for performing a predetermined operation and a signal holding circuit for holding a signal from the microprocessor as an analog signal. More specifically, the present invention relates to a microprocessor device capable of holding the output of a signal holding circuit immediately before an abnormal operation of a microprocessor occurs without drift when the abnormal operation of the microprocessor occurs.

(Prior Art) As a signal holding circuit for holding a signal from a conventional microprocessor as an analog signal, a sample and hold circuit using a capacitor is used, and when an abnormal operation of the microprocessor is detected, The hold switch is turned off to hold the output signal immediately before the capacitor malfunctions.

(Problems to be Solved by the Invention) However, the capacitor configured to hold a signal has a problem that the value of the signal slightly changes due to a leakage current when the state is maintained for a long time.

The present invention has been made in view of such problems, and an object thereof is to add another digital circuit to the conventional one so that the output signal can be kept long without a drift when the microprocessor malfunctions. It is to realize a microprocessor device capable of holding time.

(Means for Solving the Problem) FIG. 1 is a block diagram showing the basic configuration of the present invention. In the figure, 1 is a microprocessor for performing a predetermined operation, 2 is a signal holding circuit for holding the signal from the microprocessor 1 as an analog signal, 3 is a monitoring means for monitoring the operation of the microprocessor 1, and SW1 is this monitoring means. First switch means for disconnecting the connection between the signal holding circuit 2 and the microprocessor 1 when an abnormal operation of the microprocessor 1 is detected by 3, 4 is a counter, 5 is an analog signal from the digital signal from the counter 4. A D / A converter for converting into a signal, a comparator 6 for comparing the signal from the D / A converter 5 with a signal from the signal holding circuit 2, and a SW2 holding the signal from the D / A converter 5 It is a second switch means provided to the input side of the circuit 2.

Reference numeral 7 inputs a clock, a signal from the monitoring means 3 and a signal from the comparator 6, and while the monitoring means 3 does not detect an abnormal operation of the microprocessor 1, the counter 4 is supplied to the counter 4 until the signal from the comparator 6 is inverted. A clock is applied so that the value of the counter follows the output of the signal holding circuit 2 every predetermined period, and when the monitoring means 3 detects an abnormal operation of the microprocessor 1, the following operation is stopped and the counter 4 holds the signal holding circuit. 2 is a logic circuit that holds the output of 2 and drives the second switch SW2.

The microprocessor 1 includes a D / A converter (not shown), and the calculation result by the microprocessor is converted into an analog signal via the D / A converter.
It is configured to be applied to the signal holding means via the first switch means.

Further, the logic circuit 7 has signals (increase instruction signal INC, decrease instruction signal DE, not shown) from a manual operation means.
C) is applied, and the contents of the counter can be changed according to these instruction signals.

(Operation) While the microprocessor 1 is operating normally, the signal from the microprocessor 1 is the first switch means S.
It is output via the signal holding circuit 2 via W1. In this state, the count value of the counter 4 follows the output of the signal holding circuit 2 by the loop including the comparator 6 and the logic circuit 7.

When the microprocessor 1 malfunctions, the logic circuit 7 stops the following operation, and the count value held in the counter 4 is changed to the second switch SW2 and the signal holding circuit 2.
Output via.

Embodiments Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a configuration block diagram showing an embodiment of the present invention. In this embodiment, a controller is constructed by using a microprocessor. In the figure, the first
The same parts as those in the figure are designated by the same reference numerals. In the microprocessor 1, 11 is a calculation control unit (CP
U) and 12 are ROs storing various programs and data
M and 13 are RAMs for storing data and arithmetic expressions, and 14 is an input / output port, which are connected to each other via a bus. Reference numeral 15 is a comparator, which has a measurement signal PV from the process selected by the multiplexer 16 at one input terminal,
A set value (target value) signal SV is input. Reference numeral 16 is a D / A converter for converting the calculation result from the microprocessor 1 into an analog signal, and the analog signal from this is applied to the signal holding circuit 2. The output signal of the D / A converter 16 is applied to the other input terminal of the comparator 15,
An A / D conversion loop is formed when the measurement signal PV and the set value (target value) signal SV are converted into digital signals.

In the signal holding circuit 2, SO is the microprocessor 1
A sample and hold switch driven by a signal from the device, 20 is a holding capacitor, and 21 is an amplifier. Monitoring means 3 for monitoring the operation of the microprocessor 1
, A watchdog timer is used, and when it times out, it is determined that an abnormal operation of the microprocessor has occurred, the FAIL lamp is turned on, and the F
It is configured to output the AIL signal to the logic circuit 7.

The logic circuit 7 has a gate 7 for inputting a clock CLK.
1, 72, gate control circuit 7 for controlling these gates
3, a synchronization circuit 74 which inputs the FAIL signal and the clock from the monitoring means 3 and drives the second switch SW2.

Reference numeral 70 denotes a manual operation means having an increase switch INC and a decrease switch DEC, the output of which is applied to the gate control circuit 73. The manual operation means 70 is used when the output signal Vout is changed when the microprocessor 1 is in an abnormal operation state.

The operation of the device configured as described above will be described below.

FIG. 3 is a time chart showing an example of the operation.

First, it is assumed that the microprocessor 1 is operating normally. In this state, the monitoring means 3 does not time up, the first switch SW1 is connected to the contact a side (D / A converter 16 side), and the microprocessor 1 controls, for example, proportionality and integration. The calculation result is the analog signal Vout from the signal holding circuit 2 via the D / A converter 16 and the first switch SW1 (d).
It is output as shown in.

The output signal Vout of the signal holding circuit 2 is also applied to one input end of the comparator 6, and the logic circuit 73 opens the clock CLK, for example, the gate 71 until the signal from the comparator 6 is inverted. , And to the UP terminal of the counter 4. The counter 4 counts the applied clock, and D
The / A converter 5 converts this into an analog signal Vd,
The voltage is applied to the other input terminal of the comparator 6.

The count value of the counter 4 increases as shown in (f), and D /
When the output Vd of the A converter 5 becomes equal to the output signal Vout from the signal holding circuit 2, the output of the comparator 6 is inverted as shown in (g).

The logic circuit 7 receives the inverted signal from the comparator 6, stops the supply of the clock to the counter 4, and holds the count value of the counter 4 as shown in (f). This counter 4
The count value of is reset every fixed period T by the reset pulse shown in (e) obtained by dividing the clock shown in (b).

When the microprocessor 1 operates normally, a loop formed by the counter 4, the D / A converter 5, the comparator 6, and the logic circuit 7 causes the counter 4 to output the output signal Vout of the signal holding circuit 2 at regular intervals. The digital signal following the is held.

When an abnormality occurs in the operation of the microprocessor 1 from such a state, the monitoring means 3 detects it and outputs a FAIL signal as shown in (a) and the first switch S.
W1 is driven from the contact a side to the contact b side (disconnecting the output from the microprocessor 1) as shown in (h).

Upon receiving the FAIL signal from the monitoring means 3, the gate control circuit 73 causes the counter 4 to output the output Vou of the signal holding circuit 2.
When the digital signal corresponding to t is held, the loop formed by the counter 4, the D / A converter 5, the comparator 6, and the logic circuit 7 is released. Further, when the synchronizing circuit 74 receives the FAIL signal from the monitoring means 3, it drives the second switch SW2 to be turned on as shown in (i) until the FAIL signal disappears from the next cycle.

When the second switch SW2 is turned on, the digital signal held in the counter 4 (this digital value corresponds to the output Vout of the signal holding circuit 2 immediately before the first switch SW1 is driven) is D / A. It is converted into an analog signal through the converter 5 and given to the input side of the signal holding circuit 2.

Therefore, the output signal V from the signal holding circuit 2 in this state
Since out is digitally held by the counter 4, it does not drift for a long time.

In such a state, the switch I of the manual operation means 70
When the NC or DEC is operated, the gate control circuit 73 receives this and sends the clock to the UP terminal of the counter 4 or
Apply to DN terminal. Therefore, the value of the output signal Vout from the signal holding circuit 2 can be manually changed.

Although the comparator 6 is configured to input the output voltage of the amplifier 21 of the signal holding circuit 2 in the above embodiment, the voltage of the holding capacitor 20 may be input.

Further, the output Vd obtained by D / A converting the digital signal of the counter 4 is applied to the input side of the signal holding circuit 2 via the second switch and the first switch SW1, but the second switch SW2 is Alternatively, it may be directly applied to the input side of the signal holding circuit 2 via.

(Effects of the Invention) As described in detail above, according to the present invention, a microprocessor device capable of holding an output signal of a signal holding circuit for a long time without drift when the operation of the microprocessor becomes abnormal. Can be realized.

Further, in the present invention, in addition to the first D / A converter for converting the calculation result from the microprocessor into an analog signal, a second D / A converter for converting the signal from the counter into an analog signal is provided. When the microprocessor is malfunctioning, a signal corresponding to the content of the counter is output via the counter, the second D / A converter, the second switch means, and the signal holding circuit. is there. Therefore, even if the first D / A converter associated with the microprocessor fails, the second D / A converter may be used instead of the second D / A converter.
A signal corresponding to the content held in the counter is output via the D / A converter of No. 3, and even in this case, there is a special effect that an accurate held signal can be output.

[Brief description of drawings]

FIG. 1 is a block diagram showing the basic configuration of the present invention, and FIG.
FIG. 3 is a configuration block diagram showing an embodiment of the present invention, and FIG. 3 is a time church showing an example of its operation. 1 ... Microprocessor 2 ... Signal holding circuit 3 ... Monitoring means 4 ... Counter 5 ... D / A converter 6 ... Comparator 7 ... Logic circuit SW1 ... First switch SW2 ... Second Switch

Claims (1)

[Claims] 1. A microprocessor for performing a predetermined operation, a first D / A converter for converting an operation result by the microprocessor into an analog signal, and an analog signal from the first D / A converter. Signal holding means for holding, monitoring means for monitoring the operation of the microprocessor, and between the signal holding circuit and the first A / D converter when an abnormal operation of the microprocessor is detected by the monitoring means , A counter, a second D / A converter for converting a digital signal from the counter into an analog signal, a signal from the second D / A converter, and A comparator for comparing the signal from the signal holding circuit, a second switch means for applying the signal from the D / A converter to the input side of the signal holding circuit, and a clock Logic for inputting a signal from the monitoring means, a signal from the comparator, and a signal from the manual operation means for instructing an increase or a decrease, controlling a clock applied to the counter, and controlling a second switch means. The logic circuit includes a circuit, and while the monitoring unit does not detect an abnormality in the operation of the microprocessor, clocks the counter until the signal from the comparator is inverted, and the value of the counter holds the signal at predetermined intervals. When the monitoring means detects an abnormal operation of the microprocessor so as to follow the output of the circuit, the following operation is stopped, the counter holds the output of the signal holding circuit, and the content of the counter is changed from the manual operation means. The signal from the second D / A converter can be changed by driving the second switch means. Microprocessor unit and controls to be applied to the lifting circuit.