JPH0132126Y2 - - Google Patents

Description

[Detailed description of the invention] The present invention provides protection for a counter memory system using a backup power source, which eliminates the inconvenience that the count counted in the counter using a backup power source changes when the power is turned on or off. Regarding circuits.

With the spread of microcomputers, counters that use backup power supplies are opening up a wide range of application fields as peripheral memory.

By the way, a counter memory that uses a backup power source uses this backup power source to store the information counted by the counter for a certain period of time, but noise is generated in the input signal line of the counter when the power is turned on or turned off. The disadvantage is that the information in the counter changes as a result.

The present invention has been developed in view of the above points, and is a counter that uses a backup power source and protects the information in the counter by keeping the counter's input signal line at a low level during power fluctuations such as when the power is turned on or off. It provides a protection circuit for memory systems, and its gist is as follows:
Connect the output signal terminal of a T-type flip-flop to the input signal terminal of a counter using a backup power supply, create a power supply whose timing is shifted from the main power supply, input this power supply and the main power supply to generate a signal, and generate a signal using this power supply and the main power supply as inputs. A signal is input and connected to the clear terminal of the T-type flip-flop, and the main power is turned on/off.
The present invention relates to a protection circuit for a counter memory system using a backup power supply, which is characterized by keeping the input signal line of the counter at a low level when the power is cut off.

Hereinafter, the present invention will be explained in detail based on the drawings.

Fig. 1 is a block diagram showing an embodiment of a counter memory using a backup power source of the present invention and its protection circuit, Fig. 2 is a time chart of the protection circuit,
FIG. 3 is a circuit diagram showing an example of obtaining Vcc ₁ delayed with respect to main power supply Vcc ₂ . In FIGS. 1 to 3, 1 is a T-type flip-flop, 2 is a counter,
3 is a high capacity capacitor, 4 and 5 are inverters, a time constant circuit consisting of a capacitor 6 and a resistor 7 is connected between the inverters 4 and 5, and a connection point 8 between the capacitor 6 and the resistor 7 is is connected to one end of the resistor 9 and the diode 10 of opposite polarity connected in parallel, and to the anode of the diode 12 via the resistor 11, and to the other end of the resistor 9 and the diode 10 of opposite polarity connected in parallel. is connected to the power supply Vcc ₁ , and the cathode of the diode 12 is connected to the main power supply Vcc ₂ . In addition, each of the input sides of the T-type flip-flop 1, counter 2, and inverter 4 has a power supply.
Vcc ₁ is connected. Note that there is a timing difference between the power supply Vcc ₁ and the main power supply Vcc ₂ at the time of rise and fall as shown in Figure 2, and the power supply
The timing difference between Vcc ₁ and main power supply Vcc ₂ is the third
This can be obtained from the circuit diagram, an example of which is shown in the figure.
Then, the power supply having such a timing shift is supplied to the T-type flip-flop 1, the counter 2, the inverter 4, the cathode of the diode 12, etc.

In the counter memory constructed in this manner and using a backup power source, the clock pulses input to the T-type flip-flop 1 are counted in binary and inputted to the counter 2 from the input signal line, and the counter 2 sequentially counts the information. I will remember it.

Now, if the main power supply Vcc ₂ is cut off due to a power outage or other cause, the potential of the power supply Vcc ₂ will instantly drop to 0 volts, and after time t ₁ has passed, the potential of the power supply Vcc ₁ will drop to 0 volts. The potential at connection point 8 is the main power supply
Since it falls to a low level when the potential of _Vcc2 falls to 0 volts, an inverted high level output appears at the output of the inverter 5 and is supplied to the clear terminal of the T-type flip-flop 1. Therefore, the T-type flip-flop 1 is prohibited from counting, and the power supply of the T-type flip-flop 1 is disabled.
The clock pulses inputted until Vcc ₁ is cut off with a time delay are counted in binary and are no longer output.

Therefore, the counter 2 retains the count information immediately before the main power supply is cut off by the energy from the high-capacity capacitor 3. Then, when the voltage of the power supply Vcc ₁ drops to 0 volts, the T-type flip-flop 1,
Since the inverter 5 is in a non-operating state, the information written in the counter 2 is stored in a non-volatile manner while energy is supplied from the high capacity capacitor 3.

Afterwards, when the cause of the power interruption, such as a power outage, is recovered and the main power supply Vcc ₂ is turned on, the T-type flip-flop 1 and counter 2 become operational, but the input level of the inverter 4 becomes a low level. Therefore, the output level of inverter 4 becomes high level, and the level of connection point 8 via capacitor 6 is also low level, so an inverted high level output appears at the output level of inverter 5, and T
It will be supplied to the clear terminal of the type flip-flop 1. Therefore, the T-type flip-flop 1
count is prohibited and will not work.
Then, the power supply Vcc ₁ rises sufficiently after time t ₂ has elapsed, and the input side of the inverter 5 becomes high level, and an inverted low level output appears at the output of the inverter 5, and the clear terminal of the T-type flip-flop 1 is output. will be supplied to Therefore, the T-type flip-flop 1 counts the clock pulses in binary and writes the output into the counter 2 from the input signal line.

In this way, counting of the T-type flip-flop 1 is temporarily prohibited when the main power supply Vcc ₂ is cut off or turned on, thereby preventing the count number of the information counted by the counter 2 from changing.

Next, another embodiment of the present invention will be described with reference to FIGS. 4 and 5. FIG. 4 shows another embodiment of the protection circuit in the counter memory system using a backup power source according to the present invention, and the same components as those in the previous embodiment are given the same reference numerals and their explanation will be omitted. Further, the timing difference between the power supply Vcc ₁ and the main power supply Vcc ₂ is obtained from the circuit diagram shown in FIG. 3 as an example. A diode 20 of opposite polarity is connected to the clear terminal of the T-type flip-flop 1 in this embodiment.
The output side of EXOR21 is connected via
The input side of this EXOR21 is the power supply Vcc ₁ and the main power supply.
Vcc ₂ are connected via resistors 22 and 23, respectively. Further, the anode of the diode 20 is connected to the power supply Vcc ₁ via a resistor 24. In the figure, 25 is a connection point between the anode of the diode 20 and the resistor 24.

When the main power supply Vcc ₂ is cut off due to a power outage, etc., _the counter memory configured in this way and using a backup power supply instantly drops to 0 volts.
The power supply Vcc ₁ drops to 0 volts with a delay of time t ₃ . For this reason, EXOR2 at the moment the power is cut off
Since a high level output appears on the output side of 1, the voltage appearing at the connection point 25 from the power supply Vcc ₁ via the resistor 24 is supplied to the clear terminal of the T-type flip-flop 1, inhibiting the counting of the T-type flip-flop 1. And the power supply Vcc ₁ of T-type flip-flop 1
The clock pulses inputted until the clock pulse is cut off with a delay of time _t3 are no longer counted in binary.

Therefore, the counter 2 retains the information (count number) just before the power is cut off by the energy from the high capacity capacitor 3.
When the voltage of the power supply Vcc ₁ drops to 0 volts, the T-type flip-flop 1 becomes inactive, so the count information written in the counter 2 is supplied with energy from the high-capacity capacitor 3. It is stored non-volatilely while it is stored.

However, when the cause of the power cutoff due to a power outage etc. is recovered and the main power supply Vcc ₂ is turned on, T
Type flip-flop 1 and counter 2 are in the operating state, but the input of EXOR 21 is connected to the main power supply Vcc ₂
Since only the voltage of the power supply Vcc ₁ is applied and the voltage of the power supply Vcc 1 is not applied, a high level output appears at the output of the EXOR 21, and the diode 20 is reverse biased. Therefore, the voltage of the power supply Vcc ₁ appears at the connection point 25 via the resistor 24, and the voltage at this connection point 25 is applied to the clear terminal of the T-type flip-flop 1 to control the count of the T-type flip-flop 1. prohibit. And the power
When Vcc ₁ rises sufficiently after time _t4 and a high level voltage is applied to the input of EXOR21,
Since a low level output appears at the output of EXOR 21, the voltage of power supply Vcc ₁ is applied to connection point 25 through resistor 24 to forward bias diode 20. Therefore, the clear terminal of the T-type flip-flop 1 goes low, and the T-type flip-flop 1 counts the clock pulses in binary and writes its binary output to the counter 2 via the input signal line.

In this way, counting by the T-type flip-flop 1 is temporarily inhibited when the main power supply Vcc ₂ changes, such as when it is cut off or turned on, so that the count counted by the counter 2 does not change.

As described above, the protection circuit of the counter memory method using a backup power supply according to the present invention creates a power supply whose timing is shifted from the main power supply, generates a signal by inputting this power supply and the main power supply, and converts this signal into a T-type. By connecting the input to the clear terminal of the flip-flop, the input signal line of the counter is held at a low level when the main power supply is turned on and off, and the clock pulses are not counted. It is designed so that the count does not change, and can be used extremely effectively in protection circuits used in counters that memorize the stop position of elevators.

[Brief explanation of drawings]

The drawing shows a counter memory type protection circuit using a backup power supply according to the present invention.
Figure 2 is a block diagram showing one embodiment, Figure 2 is its time chart, Figure 3 is a circuit diagram showing an example of obtaining a power supply Vcc ₁ with a timing delay with respect to the main power supply Vcc ₂ , and Figure 4 The figure is a block diagram showing another embodiment, and FIG. 5 is a time chart thereof. 1: T-type flip-flop, 2: counter,
4, 5: Inverter, 21: EXOR, Vcc ₁ : Power supply, Vcc ₂ : Main power supply.

Claims (1)

[Scope of utility model registration request] Connect the output signal terminal of a T-type flip-flop to the input signal terminal of a counter using a backup power supply, create a power supply whose timing is shifted from the main power supply, input this power supply and the main power supply to generate a signal, and generate a signal using this power supply and the main power supply as inputs. A signal is input and connected to the clear terminal of the T-type flip-flop, and the main power is turned on/off.
A protection circuit for a counter memory method using a backup power supply, which is characterized by keeping the input signal line of the counter at a low level when the power is cut off.