JPH0136364Y2 - - Google Patents

Description

[Detailed explanation of the idea] <Industrial application field> The present invention relates to an integral type D/A converter.

<Conventional technology> Recently, in the audio field, audio signals (analog signals) are processed using pulse code modulation (PCM).
A system for recording and reproducing data by converting it into a digital signal has been developed by the Japanese company, and this recording and reproducing system has a configuration as shown in FIG.

The analog signal A is sampled by a sampling circuit 1 at a sampling frequency _s , and each sample value is converted into a digital signal by an A/D converter 2, and then passed through a recording side signal processing circuit 3 to a signal processing clock signal ( The signal is processed in synchronization with the signal processing clock frequency _c ) and recorded on the recording medium 4.

The signal reproduced from the recording medium 4 is processed through the reproduction side signal processing circuit 5 in synchronization with the signal processing clock signal (signal processing clock frequency _c ), and then passed through the data transfer circuit 6 to the integral type D/A converter 7. be transferred. The output signal of this integral type D/A converter 7 is converted into the original analog signal A by a low pass filter 8.

The integral type D/A converter 7 obtains a time width proportional to the input data by counting clock signals corresponding to the numerical value given by the input data, integrates a constant current during that period, and converts the input It is designed to obtain an analog voltage value corresponding to data. This integral type D/A converter 7
As shown in FIG. 1, a charging/discharging circuit 12 includes a digital comparator 8, a counter 9, a constant current source 10, a first switch 11, and an integrating capacitor 13, and a charging/discharging circuit 12 that controls charging and discharging of the integrating capacitor 13. It is composed of two switches 14 and a control circuit 15.

A control signal from the control circuit 15 turns on the second switch 14 to discharge the integrating capacitor 13, and then, at the same time as the second switch 14 turns off, the reset counter 9 is turned on by the control circuit 15. Then, the first switch 11 is turned _on , the constant current source 10 becomes operational, and the integrating capacitor 13 starts to be charged. When the count number of the counter 13 matches the numerical value of the input data, a stop signal is output from the digital comparator 8, which turns off the first switch 11 and stops charging the integrating capacitor 13. Integrating capacitor 13 until charging starts regenerating by the next control signal.
The charge is held, and the charge/discharge circuit 12 outputs a voltage proportional to the charge of the integrating capacitor 13, that is, the input data.

Also, from the reproduction side signal processing circuit 5, an integral type D/A
Data transfer to converter 7 is performed in synchronization with a data transfer clock signal (data transfer clock frequency _t ).

Specifically, in a so-called digital audio recording and reproducing system that handles audio signals, the following is defined.

Sampling frequency _s = 44.1KHz Signal processing clock frequency _c = 8.6436MHz Data transfer clock frequency _t = 1/4 _c = 2.1609MHz Clock frequency _D = 41.0MHz <Problems to be solved by the invention> Recording and reproducing system as described above Now, in the integral type D/A converter 7 section, interference occurs between the harmonic components of the data transfer clock signal and the clock signal, and the frequency difference between the two signals becomes _p = | _D - m・_t | A difference component is generated, and an unnecessary signal component is generated in the audio signal band due to the aliasing phenomenon peculiar to PCM.

The aliasing phenomenon is, for example, as shown in Figure 3, for the difference component _p1 , the mapping ′ _p1 = _s /2−( _p1 − _s /2) = _s − _p1 is created with _s /2 as the axis. It also refers to the phenomenon in which the mapping ′ _p2 = _s − ( _p2 − _s ) = 2 _s − _p2 occurs with _s as the axis for the difference component _p2 .

In FIG. 3, symbol B is an audio signal band.

In general, the frequency of noise outside the audio signal band is _p , and the frequency of the mapping of noise generated within the audio band due to the aliasing phenomenon is ′ _p
Then, when 2n+1/2・_s < _p <2n+3/2・_s , ′ _p =|(n+1) _s − _p | n=0, 1, 2,...

For example, when n=0, _s /2< _p <3/2 _s ,' _p = | _s − _p |, and when n=1, 3 _s /2< _p <5/2 _s ,' _p = |2 _s − _p |, as shown in Figure 3.

Specifically, in the above digital audio playback system, the clock frequency _D (41.0MHz) of the D/A converter and the data transfer clock frequency _t
(2.1609MHz), a frequency difference component of _p = |41.0−19×2.1609|[MHz] =57.1[KHz] is generated, and this is caused by the aliasing phenomenon as ′ _p = _p − _s = 57.1 An interference signal of −44.1 = 13 [KHz] is generated in the audio signal band.

The present invention aims to solve these conventional drawbacks.

<Means for solving the problem> The present invention provides input data in synchronization with a predetermined data transfer clock signal, and counts the clock signal by the number corresponding to the numerical value given by the input data. Obtain a time width proportional to the input data, integrate the constant current during that period,
In a D/A converter designed to obtain an analog voltage value corresponding to the above input data, the frequency _D of the above clock signal is _D = m・_t +2n+1/2・_s (m=1, 2, 3,... n= 0, 1, 2, . . .) where _t : the frequency of the data transfer clock signal _s : the sampling frequency of the original analog signal corresponding to the input data is set.

<Effect> As a result, the frequency of the difference component between the harmonic components of the D/A converter clock signal and the data transfer clock signal is an odd multiple of the frequency of 1/2 of the sampling frequency _s (2n+1/2・_s (n=0, 1, 2,…) becomes. Therefore, since the mapping of the difference component does not occur with _s /2 as the axis, no interference signal due to the aliasing phenomenon occurs in the audio signal band.

<Example> This will be explained in FIG.

Clock signal _D (frequency _D ) supplied to counter 9 of D/A converter 7 and data transfer circuit 6
The difference component between the data transfer clock signal _t (frequency _t ) and the harmonic component m・_t is the difference component with the frequency _p = | _D − m・_t | (m = 1, 2, ...) ...(1) Becomes an ingredient.

Here, as is clear from Fig. 3 showing the aliasing phenomenon, the frequency _p of the above difference component is _p = 2n + 1/2 _s (n = 0, 1, 2,...) ... (2) where _s : input data By setting the sampling frequency of the original analog signal corresponding to , there is no mapping around _s /2, and it is possible to prevent the generation of interference signals due to the aliasing phenomenon.

Therefore, from equations (1) and (2), the frequency _D of the clock signal _D of the D/A converter is _D = _m.t + 2n + 1/2 _s (3).

That is, the clock frequency _D is determined to be within the operating range of the D/A converter and to satisfy equation (3).

Specifically, when the data transfer clock frequency _t and sampling frequency _s are given as _t = 2.1609MHz _s = 44.1KHz, _D = 40.05315MHz with m = 19 and n = 0, and the clock frequency _D of the D/A converter is
It is sufficient to set it to 40.05315MHz.

<Effect of the invention> According to the above configuration, the frequency of the difference component between the clock signal and the harmonic component of the data transfer clock signal is an odd multiple of 1/2 of the sampling frequency.
No interfering signals due to aliasing occur in the audio signal band.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of an integral type D/A converter of the present invention, FIG. 2 is a diagram showing the configuration of a PCM recording and reproducing system, and FIG. 3 is a diagram showing the aliasing phenomenon. 6 is a data transfer circuit, and 7 is an integral type D/A converter.

Claims (1)

[Claim for Utility Model Registration] Input data is supplied in synchronization with a predetermined data transfer clock signal, and by counting the clock signal by the number corresponding to the numerical value given by the input data, In a D/A converter that obtains a time width and integrates a constant current during that period to obtain an analog voltage value corresponding to the input data, the frequency _D of the clock signal is set as _D = m・_t +2n+1/2・_s (m = 1, 2, 3, ... n = 0, 1, 2, ...) However, _t : Frequency of the data transfer clock signal _s : Set to the sampling frequency of the original analog signal corresponding to the input data A D/A converter characterized by: