JPH0136734B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a sample-and-hold output signal analog signal conversion circuit that converts a staircase wave signal obtained by a sample-and-hold circuit into an analog signal.
This invention relates to a circuit for converting sample-and-hold output signals into analog signals that can be used in stereo demodulation circuits of FM tuners, etc.

For example, in a stereo demodulation circuit of an FM tuner, especially a sampling-and-hold stereo demodulation circuit, the sampled and held left and right channel signals have a staircase waveform, and the components of the sampling pulse included in the staircase waveform, the input signal, and the sampling In order to remove sideband components caused by multiplication with pulses,
I had a problem that required a filter.

The present invention has been made in view of the above, and an object of the present invention is to provide an analog output circuit for a sample-and-hold output signal, which can be used in a stereo demodulation circuit of an FM tuner, for example, and can omit the above-mentioned filter. It is.

The present invention will be explained below with reference to Examples.

FIG. 1 is a block diagram of one embodiment of the present invention.

In Fig. 1, 1 is a signal source, 2, 5,
Buffer amplifiers 8, 11 and 13 have a high slew rate, high input impedance, and low output impedance. 3 is a two-phase pulse oscillator that generates two sampling pulse trains having a phase difference. 4, 6, 9 and 17 are switch circuits consisting of electronic switches such as CMOS analog switches or field effect transistors,
The switch circuits 4, 9 and 17 are turned on and off by the sampling pulse of the first sampling pulse train output from the two-phase pulse oscillator 3, and the switch circuit 6 is turned on and off by the sampling pulse of the first sampling pulse train output from the two-phase pulse oscillator 3. Turned on and off by sampling pulse. The switch circuit 4 together with the capacitor 12 constitutes a staircase wave generating circuit U consisting of a sample and hold circuit that samples and holds the signal from the signal source 1 and converts it into a staircase wave signal whose amplitude changes at regular time intervals. The switch circuit 6, together with the capacitor 7, is a first delay circuit V consisting of a sample and hold circuit that samples and holds the staircase wave signal from the staircase wave generation circuit U input through the buffer amplifier 5 and delays it.
It consists of Switch circuit 9 is capacitor 1
0 as well as a second delay circuit W consisting of a sample and hold circuit that samples and holds the staircase wave signal input through the buffer amplifier 8 and delays it.
It consists of Two delay circuits, a delay circuit V and a delay circuit W, delay the staircase wave signal from the staircase wave generation circuit U by one cycle of the amplitude change of the staircase wave signal, that is, one cycle of the sampling pulse of the first sampling pulse train.

14 is an inverting circuit; 15 is an inverting circuit that passes the staircase wave signal output from the staircase wave generation circuit U input through the buffer amplifier 13 and the staircase wave signal output from the second delay circuit W through the buffer amplifier 11; This is a first adder that adds the signals inverted by 14. Reference numeral 16 denotes an integrating circuit, and the integrating circuit 16 and the switch circuit 17 constitute an integrating circuit with a reset function whose integrated output is reset by the switch circuit 17 for each sampling pulse of the first sampling pulse train.

18 is a second adder circuit which adds the output signal of the second delay circuit W input through the buffer amplifier 11 and the output signal of the integration circuit 16, and outputs the sum to the output terminal OUT.

The operation of the present embodiment configured as described above will be explained by taking as an example the case where the present embodiment is applied to a sampling-and-hold type stereo demodulation circuit.

In this case, the signal source 1 is converted into a low output impedance signal source by the buffer amplifier 2, and the FM composite signal shown in FIG. 2a is input from the signal source 1 to the staircase wave generation circuit U via the buffer amplifier 2. Ru. Also, in Figure 2 a, the solid line is 38KHz.
The broken line indicates one channel component of the stereo audio component, and the dashed line indicates the other channel component. The two-phase pulse oscillator 3 is synchronized in phase with the pilot signal included in the FM composite signal output from the signal source 1, and generates a first sampling pulse train shown in FIG. 2b for separating the left channel signal from the FM composite signal. and a second sampling pulse train shown in FIG. 2c for separating the right channel signal, a pair of 38 KHz sampling pulse trains having a phase difference of 180 degrees from each other are output.

It is assumed that the switch circuits 4, 6, 9, and 17 are turned on when the applied sampling pulse is at a high potential, and turned off when the sampling pulse is at a low potential.

Therefore, the sampling pulse shown in FIG. 2b is applied to the staircase wave generating circuit U, and when each pulse has a high potential, the switch circuit 4 is turned on, and the capacitor 12 is connected to the sampling pulse shown in FIG. It is charged to the level of the FM composite signal at that point in time. When the sampling pulse becomes a low potential, the switch circuit 4 is turned off. However, the buffer amplifiers 5 and 13 connected to the output terminal of the staircase wave generation circuit U have high input impedance, and the capacitor 12 and the buffer amplifier 2
Since the electric charge stored in the capacitor 12 is kept unchanged until the next sampling pulse becomes a high potential, the potential of the capacitor 12 is transmitted to the subsequent stage via the buffer amplifiers 5 and 13. In addition, in this case, since the purpose is to demodulate only the envelope of the FM composite signal, the width of the sampling pulse that turns on the switch circuit 4 is narrow and the off period is long, but as mentioned above, the potential of the capacitor 12 is maintained during the off period. held,
The output of the staircase wave generating circuit U becomes the staircase wave signal shown in FIG. 2d. This staircase waveform is the same as the output waveform of a sample-and-hold circuit in a sampling-and-hold type stereo demodulation circuit.

The output of the staircase wave generating circuit U shown in FIG. 2d is applied to the first delay circuit V through the buffer amplifier 5. The buffer amplifier 5 converts the potential of the capacitor 12 into a low output impedance signal source as an input signal. On the other hand, the switch circuit 6
It is turned on and off by the sampling pulse of the sampling pulse train, that is, the sampling pulse shown in FIG. 2c. Therefore, the capacitor 7 is charged to the potential of the staircase wave signal shown in FIG. 2d at the time of generation of the sampling pulse shown in FIG. 2c,
This is held until the next sampling pulse is generated, and the potential of the capacitor 7 becomes a stepped potential for each period of the sampling pulse shown in FIG. 2c. However, since the sampling pulse of FIG. 2c has a phase difference of 180 degrees with respect to the sampling pulse of FIG. 2b, the output signal of the first delay circuit V is as shown in FIG. Figure 2 d is delayed by only 1/2 period of the amplitude change period of the staircase wave signal output from the staircase wave generation circuit U shown in Figure 2 d.
It becomes a staircase wave signal with the same shape as .

Furthermore, during this delay, when the switch circuit 6 is in the OFF state and the capacitor 7 holds charge, the buffer amplifier 8 has a high input impedance, so the charge in the capacitor 7 is not reduced, and the When a sampling pulse is generated, if the staircase wave signal applied as an input signal is lower than the potential at the time of generation of the immediately preceding sampling pulse, the capacitor 7
The charge will be sucked into the buffer amplifier 5 through the switch circuit 6. Therefore, even if the width of the sampling pulse is narrow, if the on-resistance of the switch circuit 6 is small, the input impedance of the buffer amplifiers 5 and 8 is high and the output impedance is low, so that the capacitor 7 is completely set to the potential of the input staircase wave signal. Even if the staircase wave signal waveform applied to the first delay circuit V is a waveform with sharp rises and falls, the delayed staircase wave signal The waveform of is delayed without being distorted.

In addition, the second delay circuit W operates in the same manner as the first delay circuit V described in detail above, so that the waveform of the first delay circuit W shown in the waveform of FIG. Delays the output staircase signal. In this case, the sampling pulse that turns on and off the switch circuit 9 of the second delay circuit W is the sampling pulse shown in FIG. 2b, and this sampling pulse turns on and off the switch circuit 9 of the second delay circuit W. Since there is a phase difference of 180 degrees with the sampling pulse of the switch circuit 6, the second delay circuit W
As a result, the staircase wave signal shown in FIG. 2f, which is obtained by delaying the staircase wave signal shown in FIG. 2e by 180 degrees, is output.
Therefore, the staircase wave signal outputted from the second delay circuit W is the staircase wave signal outputted from the staircase wave signal generation circuit U for one period of amplitude change, that is, the sampling pulse of the first sampling pulse train shown in FIG. 2b. It becomes a staircase waveform delayed by one period.

Then, the output of the second delay circuit W is sent to the inverting circuit 1.
4, and added to the output of the staircase wave generation circuit U outputted via the buffer amplifier 13 in the first adder 15. In other words, it is equivalent to being subtracted because it is inverted and added,
The first adder 15 outputs a staircase wave signal shown in FIG. 2g, which is obtained by subtracting the staircase wave signal in FIG. 2f from the staircase wave signal in FIG. 2d.

The output signal of the first adder 15 is determined by how many steps there are between a certain time on the output signal waveform of the second delay circuit W shown in FIG. This shows whether a potential difference occurs in the wave signal. That is, Fig. 2g
The potential of (E) shown in Figure 2 f is equal to the difference between the potentials of (A) and (B) [(B) - (A)], and the potential of (O) is [(C) - (A)]. ]
The potential is .

The output signal of the first adder 15 is integrated by the integrator 16, and since the switch circuit 17 is turned on and the integrator 16 is reset every period of the sampling pulse shown in FIG. The output of the device 16 has a sawtooth waveform as shown in FIG. 2h.

The output of the integrator 16 is added to the output of the second delay circuit W in a second adder 18. That is, the staircase wave signal of the second delay circuit W shown in FIG. 2f and the output of the integrator 16 shown in FIG.
are added by an adder 18. Therefore, the output of the second adder 18 is as shown in FIG. 2i, which is the output staircase wave signal of the staircase wave generation circuit U shown in FIG. 2d, that is, the FM composite signal in the sampling-hold stereo demodulation circuit. The result is similar to the output signal obtained by passing one channel signal sampled and held through a low-pass filter.

Therefore, according to this embodiment, the low-pass filter in the sampling-and-hold type stereo demodulation circuit can be omitted.

In addition, in a sampling-and-hold type stereo demodulation circuit, the amplifier provided between the sampling-and-hold signal and the low-pass filter is used to generate a staircase wave signal, which is conventionally required, because the output signal is output as an analog signal according to this embodiment. There is no need for a high-slew-rate amplifier that is required to amplify the signal, and the signal can be amplified without distortion and transmitted to the subsequent stage using a simple amplifier.

Further, although the stereo demodulation circuit has been described above as an example, the generality is not lost by this, and according to this embodiment, a sampled and held output signal can be converted into an analog signal.

As explained above, according to the present invention, a staircase wave signal can be changed into an analog signal.

Therefore, by applying the present invention to a stereo demodulation circuit, the amount of sampling pulse components remaining on the output waveform is reduced, and at the same time, a low-pass filter is added to reduce sideband components around the sampling pulse. There's no need.

Furthermore, since the output waveform is an analog signal, there is an advantage that the subsequent stage amplifier can be a simple amplifier.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention. Second
The figure is a waveform diagram for explaining the operation of an embodiment of the present invention. 2, 5, 8, 11 and 13... Buffer amplifier, 3... Two-phase pulse oscillator, 4, 6, 9 and 17... Switch circuit, 14... Inverting circuit, 15
and 18...first and second adders, 16
. . . an integrator, U . . . a staircase wave generating circuit consisting of a sample and hold circuit, V and W . . . first and second delay circuits consisting of a sample and hold circuit.

Claims (1)

[Claims] 1. A staircase wave generation circuit that samples and holds an input signal and outputs a staircase wave signal whose amplitude changes at regular time intervals, and the output staircase wave signal of the staircase wave generation circuit is converted into one cycle of the sampling pulse for the sample and hold. a delay circuit for delaying the output of the staircase wave signal by the amount of time, subtraction means for subtracting the output staircase wave signal of the delay circuit from the output staircase wave signal of the staircase wave generation circuit, and an integral for integrating the output signal of the subtraction means for each cycle of the sampling pulse. A circuit for converting a sample-and-hold output signal into an analog signal, comprising: means for converting a sample-and-hold output signal into an analog signal; and an adding means for adding the output signal of the integrating means and the output staircase wave signal of the delay circuit.