JPH0136954B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to an automatic piano performance device, and in particular,
The present invention relates to a malfunction prevention method for preventing malfunctions caused by noise, etc.

In recent years, automatic piano performance devices that automatically play the piano have been developed. In this device, each key of the piano is provided with a key-driving solenoid, and these solenoids are driven based on performance data stored in a storage unit such as a cassette tape or floppy disk. According to
It plays the piano automatically.

By the way, if the internal circuit of this automatic piano performance device malfunctions due to noise etc., a musical tone other than the musical tone stored in the memory section may be generated, or in the worst case, a signal may be applied to the solenoid for longer than the allowable time. , the problem of burning out the solenoid occurs.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a method for preventing malfunctions in an automatic piano performance device, which can prevent malfunctions of operators due to noise or the like.

Note that in this invention, the operator is a general term for piano keys and pedals.

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing the structure of an automatic piano performance device to which the method according to the present invention is applied. In this figure, reference numeral 1 indicates a key driving solenoid provided close to each key, and the circuit shown in this figure drives these solenoids based on the performance data stored in the storage section 2. , which automatically plays the piano.

That is, in this figure, code 3 is the key address SAD for specifying the key and the solenoid drive data for driving the solenoid 1.
This is a data output circuit that outputs SKD in time-sharing order in the order of progression of the music, and is composed of a storage section 2, an operation section 4, and a control circuit 5. The storage unit 2 is a memory in which performance data for driving each solenoid 1 is stored in advance in the order in which the music progresses. here,
The performance data stored in the storage section 2 will be explained. First, the performance data that specifies key-on
As shown in FIG. 2A, ED-1 is composed of an on/off identification code "1", a key code KC, keystroke strength data SD, and time data TD. In this case, the keystroke strength data SD is data corresponding to the keystroke strength of the key, that is, the driving speed of the plunger of the solenoid 1, and the time data TD is data regarding the time at which the key should be driven. On the other hand, the performance data ED that specifies key-off
-2, as shown in Figure 2B, the on/off identification code “0”, the key code KC, and the time data.
Consists of TD. Then, in the storage unit 2,
These performance data ED are sequentially stored in performance order.

The operator 4 includes a start switch for instructing the start of automatic performance, a stop switch for instructing the stop of automatic performance, a volume switch for instructing the volume, etc. The output of each switch is sent to the control circuit 5. Supplied.

The control circuit 5 sequentially reads the performance data ED from the storage section 2, and based on the read performance data ED,
This circuit outputs the key address SAD (7 bits) and the solenoid drive data SKD (8 bits) in a time-division manner, and also outputs the load signals LD ₁ to _{LD 3} . In this case, the solenoid drive data SKD is data created based on the keystroke strength data SD, and its most significant bit (MSB) is the bit that instructs solenoid 1 to turn on/off, and the other 7 bits turn solenoid 1 on and off. This becomes the data for driving. Note that this control circuit 5 will be explained in detail later.

The latch circuit 7 (first latch circuit) latches the key address SAD or solenoid drive data SKD output from the control circuit 5 when the load signal LD ₁ is supplied to its load terminal L. is supplied to the latch circuit 8 (third latch circuit). The latch circuit 8 latches the data output from the latch circuit 7 when the load signal LD ₂ is supplied to its load terminal L, and its output is supplied to the decoder 9. The decoder 9 decodes the output of the latch circuit 8, and each output of the decoder 9 corresponds to a solenoid drive circuit 1 provided corresponding to each solenoid 1.
The signal is supplied to the enable terminal E of the first latch circuit 12 (second latch circuit).

The solenoid drive circuit 11 is composed of a latch circuit 12, a drive signal generation circuit 13, an AND gate 14, and a buffer amplifier 15, and the output of the buffer amplifier 15 is supplied to the solenoid 1. When the latch circuit 12 is supplied with a "1" signal signal to its enable terminal E, it enters a data latch enabled state, and in this state, when the load signal LD ₃ is supplied to its load terminal L, it latches the output of the latch circuit 7. do. Then, the latched data
The MSB is supplied to one input terminal of the AND gate 14, and the other 7 bits are supplied to the drive signal generation circuit 13.
supply to The drive signal generation circuit 13 generates a solenoid drive signal with a constant period having a pulse width corresponding to the data supplied from the latch circuit 12, and generates a solenoid drive signal of a constant period with a pulse width corresponding to data supplied from the latch circuit 12,
Supplied to solenoid 1 via. This results in
Solenoid 1 is activated.

Next, the operation of the circuit with the above configuration will be explained.

When the operator presses the start switch of the operation section 4, the control circuit 5 first reads out the performance data ED stored at the first address of the storage section 2. here,
Assume that the read performance data ED is performance data ED-1 shown in Figure 2A, and that the key code KC of this performance data ED-1 is the key address of key F ₃ (the key of the F note of the third octave). Suppose it is SAD. Thereafter, the control circuit 5 measures the time corresponding to the time data TD of the performance data ED-1 based on the cross pulse. Then, when the time corresponding to the time data TD has elapsed, the next performance data
Read ED. Here, the read performance data ED
Assuming that is the performance data ED-2 shown in Figure 2B,
Further, it is assumed that the key code KC of the performance data ED-2 is the key address SAD of the key _F3 . From then on,
The control circuit 5 measures the time corresponding to the time data TD of the performance data ED-2, and processes the key code KC and keystroke strength data SD of the performance data ED-1 for which time measurement has been completed. That is, first, keystroke strength data SD is sent to solenoid 1.
and the on/off identification code "1" to obtain solenoid drive data SKD with MSB "1". Next, the key address SAD is output to the latch circuit 7 for a time _T1 shown in FIG.
Next, the solenoid drive data SKD is output to the latch circuit 7 for a time T ₂ (T ₂ =T ₁ ) as shown in the figure. Further, in the first half of time _T1 and the first half of time _T2 , the load signal _LD1 shown in FIG. Also,
In the latter half of time _T1 , the load signal _LD2 shown in FIG. 4C is output to the load terminal L of the latch circuit 8. Further, in the latter half of time _T2 , a load signal _LD3 shown in FIG. 4D is output to the load terminal L of each latch circuit 12. When the load signal LD ₁ is output in the first half of time T ₁ , the key address
SAD is latched in latch circuit 7. Then,
When the load signal LD ₂ is output, the same key address
SAD is latched by latch circuit 8, and this latched key address SAD is supplied to decoder 9. The decoder 9 decodes the key address SAD (the key address SAD of the key _F3 ) and outputs a "1" signal to the enable terminal E of the latch circuit 12 of the solenoid drive circuit 11 corresponding to the key _F3 . This enables the latch circuit 12. Next, when the load signal LD ₁ is output in the first half of time T ₂ , the solenoid drive data SKD is latched in the latch circuit 7 , and the latched solenoid drive data SKD is supplied to each latch circuit 12 . Then, when the load signal LD ₃ is outputted and supplied to the load terminal L of each latch circuit 12, the latch circuit 12 in the currently enabled state, that is, the latch circuit 12 in the solenoid drive circuit 11 corresponding to the key F ₃ is activated. Solenoid drive data SKD is latched. When the solenoid drive data SKD is latched in the latch circuit 12, the data latched by the latch circuit 12 is
The MSB (“1” signal) of SKD is outputted to one input terminal of the AND gate 14, and the other 7 bits are outputted to the drive signal generation circuit 13. The drive signal generation circuit 13 generates a constant cycle solenoid drive signal having a pulse width corresponding to the supplied solenoid drive data SKD, and supplies it to the other input terminal of the AND gate 14 . At this time, the AND gate 14 is in an open state because a "1" signal is supplied to one input terminal thereof. Therefore, and gate 14
The solenoid drive signal supplied to the other input terminal of the AND gate 14 and the buffer amplifier 15
is supplied to the solenoid 1 provided on the key _F3 . As a result, the solenoid 1 of the key _F3 is activated, and the key _F3 is activated.

Next, the performance data ED read out from the storage unit 2
When the time corresponding to the time data TD of -2 (time T ₃ shown in FIG. 3A) has elapsed, the control circuit 5 reads the next performance data ED from the storage section 2. From then on,
The control circuit 5 measures the time corresponding to the time data TD of the read performance data ED, and processes the performance data ED-2 for which time measurement has been completed.
That is, key-off is detected based on the on/off identification code "0", and solenoid drive data SKD with MSB "0" is created. Next, as in the case described above, the key address SAD of the performance data ED-2 (the key address SAD of the key _F3 ) and the solenoid drive data SKD are sequentially outputted, and the load signals _LD1 to _LD3 are outputted. As a result, the solenoid drive signal SKD whose MSB is "0" is read into the latch circuit 12 of the solenoid drive circuit 11 corresponding to the key _F3 , and as a result, the AND gate 14 of the solenoid drive circuit 11 is turned off.
The driving state of key F ₃ is released. Thereafter, the above-described operations are repeated and the piano is automatically played.

The above is the performance data ED read out from the storage unit 2.
This is the process in which the key is activated based on the By the way, in this automatic performance device, the following measures are taken to prevent malfunctions due to noise or the like.

That is, the control circuit 5 outputs the safe data SFD to the latch circuit 7 as shown in FIG. here,
The safe data SFD is data other than the address assigned to the key address, and is data that closes the AND gate 14 when the safe data SFD is read into the latch circuit 12. More specifically, the data is "01111111" where the MSB is "0" and all other bits are "1". Then, the control circuit 5 uses this safe data.
After outputting the SFD, load signals LD ₁ and LD ₂ are output in sequence (Figure 3 B and C), and this safe data SFD
is latched by latch circuits 7 and 8.

If such measures are taken, the following advantages can be obtained. First, the safe data SFD "01111111" latched in the latch circuit 8 is data other than the key address, so this safe data
When the SFD is supplied to the decoder 9, the decoder 9
All outputs (outputs supplied to the latch circuits 12) become "0", and all the latch circuits 12 become disabled. As a result, even if noise is induced in the signal line of load signal LD ₃ (the third
(See reference numeral _P1 in FIG. Also, for example, even if noise is induced in the signal line of the load signal LD ₂ (symbol P ₂ in Figure 3 C)
), it is the output of latch circuit 7, ie, the safe data SFD, that is latched into latch circuit 8, and therefore neither latch circuit 12 is enabled. Furthermore, for some reason, the output of latch circuit 7 (safe data
SFD) is accidentally latched by the latch circuit 12, the safe data SFD
Since the MSB is "0", solenoid 1 is only turned off. That is, it is possible to avoid the inconvenience that the solenoid drive signal is applied to the solenoid 1 for longer than the permissible time, causing the solenoid 1 to burn out.

Note that when the lower 7 bits "1111111" of the above-mentioned safe data SFD are supplied to the drive signal generation circuit 13, the circuit 13 outputs a solenoid drive signal corresponding to the weakest sound.

Further, in the above-described embodiment, only the case of driving the piano keys has been described, but the driving of the piano pedals is performed in the same manner. Therefore,
Of course, the present invention can also be applied to the case of driving piano pedals.

As explained above, according to the present invention, the first
Since safe data is stored in the latch circuit (latch circuit 7) and the third latch circuit (latch circuit 8) during the time period when the outputs of the first and third latch circuits are not used, noise etc. This provides the advantage of being able to prevent malfunctions based on

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIGS. 2A and 2B are diagrams showing the format of performance data used in the same embodiment, and FIGS.
2 is a timing chart for explaining the operation of the same embodiment. 7...First latch circuit, 8...Third latch circuit, 1
2...Second latch circuit, SKD...first data (solenoid drive data), SAD...second data (solenoid address), SFD...safe data.

Claims (1)

[Claims] 1 a first latch circuit that stores first data for driving an operator; a plurality of second latch circuits that store outputs of the first latch circuits;
a third latch circuit that stores second data for specifying one of the latch circuits; The output is memorized and
Further, in the automatic piano performance device configured such that the operator is driven based on the output of the second latch circuit, data other than the second data is input to the first latch circuit and the third latch circuit. and when the same data is stored in the second latch circuit, the safe data that causes the operator to be in a non-driving state is set during a time period when the outputs of the first and third latch circuits are not used. A method for preventing malfunctions in an automatic piano performance device characterized by memorizing the information.