JPH0136955B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an automatic musical instrument performance device that automatically plays a musical instrument, such as an automatic piano performance device.

2. Description of the Related Art As a conventional automatic piano performance device, a device is known in which performance data is recorded in advance on a cassette tape, and the performance data is read out to automatically play the piano. FIG. 1 is a diagram showing the data recording state of a cassette tape in this type of automatic piano performance device. In this diagram, a synchronization signal SYC is recorded in area _R1 , and each key in the high range is recorded in area _R2 . (key) on/off status is “1”/
A signal of “0” is recorded, the volume data of the treble range is recorded in the area R ₃ , the on/off status of each key in the bass range is recorded in the area R ₄ , and the on/off status of each key in the bass range is recorded in the area R ₅ .
The volume data of the bass range is recorded. Each piece of data recorded on this cassette tape is read out as serial data and once latched in a latch circuit, and a key is driven based on the latched data.

However, in such conventional automatic piano performance devices, since each data is recorded in bit serial format, there is a drawback in that it is not possible to specify the keystroke strength for each key. In other words, to specify the keystroke strength for each key, keystroke strength data (for example, 5 to 7 bits) is added to each "1" and "0" signal in region _R2 or _R4 . However, doing so would make the length of the region R ₂ or R ₅ enormous, making it practically impossible.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide an automatic musical instrument performance device that allows the keystroke strength of each key to be specified for each key.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a block diagram showing the configuration of an automatic piano performance device according to the present invention. In this figure, reference numeral 1 is a key drive solenoid provided close to each key, and the circuit shown in this figure is as follows:
These solenoids 1 are driven based on performance data stored in a storage section 2 to automatically play the piano.

That is, in this figure, code 3 is the key address SAD for specifying the key and the solenoid drive data for driving the solenoid 1.
This is a data output circuit that sequentially outputs SKD in the order in which the music progresses, and is composed of a storage section 2, an operation section 4, and a control circuit 5. The storage unit 2 is a memory in which performance data for driving each solenoid 1 is stored in advance in the order in which the music progresses. Here, the performance data stored in the storage section 2 will be explained. First, the performance data ED− that specifies key-on
1 is composed of an on/off identification code "1", a key code KC, keystroke strength data SD, and time data TD, as shown in FIG. 3A. In this case, the keystroke strength data SD is data corresponding to the keystroke strength of the key, that is, the driving speed of the plunger of the solenoid 1, and the time data TD is data regarding the time at which the key should be driven. On the other hand, performance data ED-2 that specifies key-off is
As shown in FIG. 3B, it is composed of an on/off identification code "0", a key code KC, and time data TD. These performance data ED are sequentially stored in the storage unit 2 in the order of performance.

The operation section 4 includes a start switch for instructing the start of automatic performance, a stop switch for instructing to stop the automatic performance, a volume switch for instructing the volume, etc. The output of each switch is sent to the control circuit 5. Supplied.

The control circuit 5 sequentially reads the performance data ED from the storage section 2, and outputs a key code SAD (7 bits), solenoid drive data SKD (8 bits), and a load signal LD (1 bit) based on the read performance data ED. It is a circuit. In this case, the solenoid drive data SKD is data created based on the keystroke strength data SD, and its most significant bit (MSB) is the bit that instructs solenoid 1 to turn on/off, and the other 7 bits turn solenoid 1 on and off. This becomes the data for driving. Then, the key address SAD mentioned above is supplied to the decoder 7, the solenoid drive data SKD is supplied to the latch circuit 10 of the solenoid drive circuit 9 provided corresponding to each solenoid 1, and the load signal
LD is supplied to the load terminal L of each latch circuit 10. Note that this control circuit 5 will be explained in detail later.

The decoder 7 decodes the key address SAD output from the control circuit 5, and each output of the decoder 7 is supplied to the enable terminal E of the latch circuit 10 of the corresponding solenoid drive circuit 9.

The solenoid drive circuit 9 includes a latch circuit 10, a drive signal generation circuit 11, an AND gate 12, and a buffer amplifier 13, and the output of the buffer amplifier 13 is supplied to the solenoid 1. When a "1" signal is supplied to the enable terminal E of the latch circuit 10, the data can be latched.
In this state, when a "0" signal is supplied to the load terminal L, the solenoid drive data SKD is latched. Then, the latched data SKD
The MSB is supplied to one input terminal of the AND gate 12, and the other 7 bits are supplied to the drive signal generation circuit 11.
supply to The drive signal generation circuit 11 receives solenoid drive data supplied from the latch circuit 10.
A solenoid drive signal with a constant period having a pulse width corresponding to SKD is created and supplied to the solenoid 1 via an AND gate 12 and a buffer amplifier 13. This drives the solenoid 1.

Next, the operation of the circuit with the above configuration will be explained.

When the operator presses the start switch of the operation section 4, the control circuit 5 first reads out the performance data ED stored at the first address of the storage section 2. here,
Assume that the read performance data ED is performance data ED-1 shown in Figure 3A, and that the key code KC of this performance data ED-1 is the key address of key F ₃ (the key of the F note of the third octave). Suppose it is SAD. Thereafter, the control circuit 5 measures the time corresponding to the time data TD of the performance data ED-1 based on the clock pulse. Then, when the time corresponding to the time data TD has elapsed, the next performance data
Read ED. Here, the read performance data ED
Assuming that is the performance data ED-2 shown in Figure 3B,
Further, it is assumed that the key code KC of this performance data ED-2 is the key address SAD of the key _F3 . From then on,
The control circuit 5 measures the time corresponding to the time data TD of the performance data ED-2, and also measures the key code KC of the performance data ED-1 for which time measurement has been completed.
and processes the keystroke strength data SD. That is, first, the keystroke strength data SD is converted according to the characteristics of the solenoid 1 to obtain solenoid drive data SKD whose MSB is "1". Next, the solenoid drive data SKD obtained by the conversion is output together with the key address SAD of the key _F3 for a certain period of time T shown in FIG. Also, at approximately the middle of the above time T, the load signal LD (“0” signal) shown in FIG.
Output. When the key address SAD of key F ₃ is output from the control circuit 5, the decoder 7 decodes this key address SAD and outputs "1" to the latch circuit 10 of the solenoid drive circuit 9 corresponding to the key F ₃ .
Output a signal. As a result, the same latch circuit 10
becomes enabled. Then the load signal
When LD is supplied to the latch circuit 10, the latch circuit 10 latches the solenoid drive data SKD, sends the MSB (“1” signal) of the latched data SKD to the AND gate 12, and sends the other 7 bits to the drive signal. Each is output to the generation circuit 11. The drive signal generation circuit 11 receives the supplied solenoid drive data.
A solenoid drive signal with a constant period having a pulse width corresponding to SKD is created and supplied to the other input terminal of the AND gate 12. At this time, AND gate 12 is in an open state because a "1" signal is supplied to one input terminal thereof. Therefore, the solenoid drive signal supplied to the other input terminal of the AND gate 12 is supplied via the AND gate 12 and the buffer amplifier 13 to the solenoid 1 provided at the key _F3 . This will cause the key
Solenoid 1 of F ₃ is activated, and key F ₃ is activated.

Next, the performance data ED read out from the storage unit 2
When the time corresponding to the time data TD of −2 has elapsed, the control circuit 5 stores the next performance data ED in the storage unit 2.
Read from. Thereafter, the control circuit 5 measures the time corresponding to the time data TD of the read performance data ED, and also measures the time corresponding to the time data TD of the performance data ED for which the time measurement has been completed.
-2 processing is performed. In other words, key-off is detected based on the on/off identification code “0”, and the MSB
Create solenoid drive data SKD with “0”. Then, transfer this solenoid drive data SKD to the key address SAD of key _F3 of performance data ED-2.
At the same time, it is output for a certain period of time T. Furthermore, the load signal LD is output approximately at the middle of the fixed time T.
As a result, the solenoid drive signal SKD whose MSB is "0" is read into the latch circuit 10 of the solenoid drive circuit 9 corresponding to the key _F3 , and as a result,
The AND gate 12 of the solenoid drive circuit 9 is turned off, and the drive state of the key _F3 is released. Thereafter, the above-described operations are repeated and the piano is automatically played.

Note that the present invention is of course applicable not only to the automatic piano performance device described above but also to automatic performance devices for other keyboard instruments.

As explained above, the automatic performance device according to the present invention includes a data output circuit that sequentially outputs key addresses and solenoid drive data, a latch circuit that is provided corresponding to each key and that latches the solenoid drive data, and a latch circuit that latches the solenoid drive data. Since the present invention includes a drive signal generation circuit that generates a solenoid drive signal based on the output of the circuit, an advantage is obtained in that the keystroke strength of each key can be specified for each key.

[Brief explanation of drawings]

Fig. 1 is a diagram showing the recording state of performance data in a conventional automatic piano performance device, Fig. 2 is a diagram showing the configuration of an embodiment of the present invention, and Fig. 3 A and B are each used in the same embodiment. Diagram showing the format of performance data, Figure 4 A to C are key addresses, respectively.
SAD, solenoid drive data SKD, load signal
5 is a diagram showing the timing at which LD is output from the control circuit 5. FIG. 1... Solenoid, 3... Data output circuit, 10...
Latch circuit, 11... drive signal generation circuit.

Claims (1)

[Claims] 1. A data output circuit that sequentially outputs key addresses corresponding to the keys to be driven and solenoid drive data corresponding to the keystroke strength of the keys in the order of progression of the music, and a key that latches the solenoid drive data output from the data output circuit. The same number of latch circuits, a drive signal generation circuit that is provided corresponding to each of these latch circuits and creates a solenoid drive signal based on the output of each latch circuit, and the output of these drive signal generation circuits. and a key drive solenoid to be driven, and the solenoid drive data output from the data output circuit is latched by the latch circuit specified by the key address output from the data output circuit. Characteristic automatic musical instrument performance device.