JPH0140932B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a method for X-Y display or X-Y recording of two types of signals that are interrelated as a function of y=f(x) and change at a particularly high speed. This relates to an X-Y display/recording storage device that is temporarily stored in a memory.

This type of device makes it possible to repeatedly display characteristic curves, such as B-H curves and material load characteristics, which are obtained on a single occasion, on a cathode ray tube, or to record them at low speed on a recorder or printer. The figure shows an example of the conventional circuit configuration. That is, in the same figure, the X-axis and Y-axis input signals are digitized by A/D converters 1 and 2, respectively, and then sent to a clock generator 9.
The write clock generated by memory 3 and 4
are written respectively. This write clock is simultaneously counted by the counter 5, and when the count value reaches 4096, which corresponds to the capacity of the memories 3 and 4, for example 4096 words, a write completion signal is generated and the output of the flip-flop 6 is inverted. This inverted output changes the memories 3, 4 from the write mode to the read mode, and the written data is held in the memories 3, 4. Then, when the clock generator 9 generates a read clock with a pulse interval for reproduction, the signals read from the memories 3 and 4 respectively are
It is converted into analog by A converters 7 and 8, and two-channel time display/recording or X-Y display/recording becomes possible.

However, as shown in FIG.
The sampling time for one word of 4, ie, the write clock Δt, is always the same pulse interval,
Moreover, since there is no circuit to stop the writing midway, when writing is started by a trigger signal, when a predetermined period of time has elapsed regardless of the input signal, that is, the memory 3,
When all addresses of 4 have been stored, a write completion signal is generated and the mode changes to read mode. On the other hand, X-Y display
In the case of recording, phenomena usually change independently of time;
Therefore, for example, as shown in Figures 3 and 4, when the input signals on the X-axis and Y-axis do not change over time, all addresses are wasted on the display/recording screen just to indicate point P. result. That is, in the conventional write method, data is sequentially written to the memory even when the input signal hardly or completely changes, and the amount of data stored is reduced by the amount of wasted data written to the memory.

Therefore, it is an object of the present invention to enable effective use of memory capacity in the storage device mentioned at the beginning.

Next, the present invention will be explained based on the embodiments shown in FIGS. 6 to 9.

FIG. 6 shows an example of a basic circuit configuration of a storage device according to the present invention, in which a comparison circuit 10 and an up-down counter 11 are connected between the output side of the A/D converter 2 and the clock generator 9 in FIG. A clock pulse and a control circuit for the counter 11 (NAND gates 12 to 14 and an inverter 15) are added. The comparison circuit 10 is an A/D
The digital output signal A of the converter 2 and the count value B of the up-down counter 11 are compared, and it is determined whether the comparison inputs A and B are balanced A=B and unbalanced A>B or A<B, and take appropriate action. "H" on the output terminal
Generates a level signal.

The output signal A generated in the A/D converter 2 in response to the X-axis input signal is determined by the comparator circuit 10 as A>B, and the corresponding output terminal is set to "H".
When a level signal is generated, NAND gates 12 and 14 are controlled to open. Therefore, the clock pulse that has passed through the NAND gate 14 is supplied to the memories 3 and 4 for use as a write clock K, and also passes through the NAND gate 12 to cause the up-down counter 11 to count up.
As a result, when the comparison input in the comparison circuit 10 is balanced, that is, when A=B, the NAND gate 14
is closed, comparator circuit 10 remains in equilibrium and the supply of write clock K is also stopped. When the level of the output signal A increases further, the up-down counter 11 generates the write clock K and
The count value is further increased to reach an equilibrium state. When the level of the output signal A decreases, A<B, and the NAND gates 13 and 14 are controlled to open. Similarly, when the write clock K is generated and the up-down counter 11 is down-counted, when this is balanced, the NAND gate 14 is closed. In other words, while the X-axis input signal remains at a constant level, the write clock K is not generated, and the write clock K is generated for each unit change in the X-axis input signal, and writing to the memories 3 and 4 is performed sequentially, increasing their storage capacity. When all are filled, the counter 5 issues a write completion signal.

When reproducing stored data, by applying a read clock with a constant pulse interval suitable for common reproduction to the memories 3 and 4, the D/A converter 8 generates an analog X-axis signal as a variable, and the D/A converter 8 generates an analog X-axis signal as a variable. The A converter 7 generates an analog Y-axis signal as a corresponding function.

The capacities of the memories 3 and 4 are determined by taking into account that the X-axis and Y-axis signals are inverted as shown in FIG.
Resolution of A/D converters 1 and 2, that is, X-axis and Y-axis
It is preferable to set it sufficiently larger than the full scale of each axis.

In addition, when inputting a special phenomenon in which the Y-axis signal changes even though the X-axis signal does not change, as shown in FIG. 8, the additional circuits 10 to 6 of FIG. Additional circuits 10' to 15' corresponding to 15 are also provided on the output side of the A/D converter, and the logical sum of the respective write clocks k and k' by the OR gate 16 is used as the actual write clock K. That is, the 8th
In the figure, when only the Y-axis signal A' changes, A
Nand gate 15 is closed due to =B, but
Due to A'>B', the Y-axis signal is written by the write clock k', and during this time, the X-axis signal of the same level is sequentially stored in the memory 4, but the Y-axis signal that gradually increases is stored in the memory 3. Ru.

As is clear from the above explanation, when one or both of the two input signals does not change during X-Y display or recording, writing to the memory is not performed, so that X-Y display or recording cannot be performed. As a result, wasteful use of memory is avoided, and storage capacity can be used effectively. Furthermore, it is possible to display and record uniform density regardless of the slowness of the signal change.

[Brief explanation of drawings]

FIG. 1 shows a conventional circuit configuration corresponding to the present invention, FIGS. 2 to 5 are explanatory diagrams of its operation, and FIGS. 6 and 9 respectively show first and second circuit configuration examples of an embodiment according to the present invention. FIGS. 7 and 8 are explanatory diagrams of the operation of the circuit configuration examples shown in FIGS. 6 and 9, respectively. 12-15, 12'-15': Control circuit.

Claims (1)

[Claims] 1. In an X-Y display/recording storage device configured to digitize two types of mutually related signals and store them in respective memories, input a clock pulse used as a common write clock for each of the memories. an up-down counter, and a comparison circuit that compares both the digitized signal A and the count value B of the counter and determines whether the inputs A and B are balanced A=B and unbalanced A>B or A<B; and a control circuit that causes the counter to count up when A>B and to count down when A<B, and to stop supplying the write clock to each of the memories when A=B. An X-Y display/recording storage device, characterized in that it is provided for both of the signals or for either one of the signals.