JPH0145784B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a multiplex data transmission system, and more specifically, a method for time-division multiplexing data from multiple lines and serially transmitting the data in a bit-multiplexed manner onto one transmission path. Related to multiple data transmission method.

Background of the Technology In devices such as data exchanges that transmit and receive data to and from a large number of terminals, data from multiple circuits is time-division multiplexed and sent to a single transmission path.

FIG. 1 shows an overview of this type of device. In the figure, MPU is a processor, MEM is a memory, DSU is a data sending unit, PRB is a processor bus, and L is a transmission line.

Then, under the control of the processor MPU, the data in the data buffer corresponding to the line set in the memory MEM is transferred to the data sending unit DSU and temporarily stored, and multiple pieces of data corresponding to multiple lines are time-division multiplexed. and sends it out to the transmission line L. At this time, the processor MPU may be operated asynchronously with the transmission line clock.

Figure 2 shows an example of data transmission in which 8-bit data is asynchronously synchronized by adding 1 parity check bit to 7 bits representing a single character (for example, a number, kana, alphanumeric character, etc.). An example of transmission is shown below.

The transmission line L exhibits two types of voltage polarity (A and Z, or 0 and 1), and transmits bits 0 and 1 with corresponding polarities. Transmission line L always shows polarity 1, and when transmitting 8-bit data representing a character in an asynchronous manner, first the start bit is
Send ST “0”, then send 8-bit data,
Furthermore, the stop bit SP “1” is sent.

For example, regarding the number 5, FIG. 2b shows 8-bit data (including a parity check bit) representing character 5, and also shows the waveform on the transmission path.

FIG. 3 is a diagram showing the principle of time-division multiplexing and transmitting data as shown in FIG. 2.

In the figure, DSU is a data sending unit and L is a transmission line, which correspond to DSU and L in FIG. 1, respectively.
The data sending unit DSU includes a multiplexer MPX, n shift registers SFR ₁ to SFR _o , and a control device.
Composed of CNT. DRU is a data receiving unit and is composed of a demultiplexer DMPX, n shift registers SFR ₁ ′ to SFR _o ′, and a control device CNT. L is a transmission path for time-division multiplexed data.

Assume now that 8-bit data of lines 1 to n (not shown) are stored in shift registers SFR ₁ to SFR _o of the data transmitter DSU as shown in the figure. That is, the data b ₁₁ to b ₈₁ of line 1 are stored in shift register SFR ₁ , and the data b _1o of line n are stored in shift register SFR 1.
b _8o is stored in shift register SFR _o .
Under the control of the control device CNT, the bit _b11 in the first bit position of the data on line 1 is first read out from the shift register _SFR1 to the multiplexer MPX, and then the bit in the first bit position of the data on line 2 is read out. b ₁₂ is read out from the shift register SFR ₂ to the multiplexer MPX, and thus from the shift registers SFR ₁ to SFR _o each bit b ₁₁ , b in the first bit position of the data of each line 1 to n ₁₂ ～
b _1o is sequentially transferred to the multiplexer MPX, where it is time-division multiplexed and sent to the transmission line L.

When the bits b ₁₁ , b ₁₂ , .about.b _1o in the first bit position of each line 1-n data are read out, the contents of the shift registers SFR ₁ -SFR _o are shifted to the right by one bit. Then, in the same way as above, bits b ₂₁ ,
b ₂₂ to b _2o are sent to the transmission line L.

Repeat the above process and shift register SFR ₁
The line 1 to n data stored in ~SFR _o is transferred to the data receiving unit DRU.

FIG. 3B shows the bit structure of data on each line 1 to n transferred through the transmission line L in this case. The data for each line 1 to n is first sent out in the order of the first bit position of each line 1 to n data, and then to the second, third to eighth bits.
The bit positions are transmitted in the order of bit lines 1 to n.

The data receiving unit DRU receives the consecutive bits shown in Figure 3B and sends them to the demultiplexer.
Separate in DMPX and shift register SFR′ ₁
Sequentially allocate one bit at a time to ~SFR′ _o . Through this process, the data in shift register SFR ₁ of the data transmitting unit DSU, b ₁₁ to b ₈₁ , are transferred to the data receiving unit.
It is stored in the shift register SFR′ ₁ of the DRU, and is stored in the shift register SFR′ 1 of the data transmitting unit DSU in the same way.
The contents of SFR ₂ to SFR _o are transferred to shift registers SFR′ ₂ to SFR′ _o of the data receiving unit DRU, respectively.
Data transfer ends.

Prior art and problems When transmitting data by time division multiplexing according to the above principle, according to the conventional technology, the fourth
This was done using the configuration shown in the figure.

FIG. 4 is a diagram showing the configuration of an example of a multiplexed data transmission system according to the prior art, and has a configuration similar to that of FIG. 1. That is, in fig.
DSU is a data sending unit, L is a transmission line, MPU is a processor, MEM is a memory, and PRB is a processor bus.

In FIG. 4, the data sending unit DSU time-division multiplexes eight pieces of 8-bit data (eight lines) and sends the data.

The data sending unit DSU is a multiplexer MPX and 8
8 shift registers corresponding to 8 lines
It has SFR ₀ to SFR ₇ .

Data buffers DB # ₀ to DB # ₇ are set in the memory MEM to store transmission information corresponding to lines 0 to 7, and character data (characters) of 8-bit codes sent from lines 0 to 7 are stored in correspondence with the lines. data buffers DB# ₀ to DB# ₇ .

To send the data (characters) of data buffers DB# ₀ to DB# ₇ in an asynchronous manner, first,
The first character data CHR ₀₁ (8 bits) of data buffer DB # ₀ corresponding to line 0 is transferred and stored in shift register SFR ₀ corresponding to line 0 under the control of processor MPU.

Next, the data buffer DB corresponding to line 1
The first character data CHR ₁₁ of # ₁ is transmitted and stored in the shift register SPR ₁ corresponding to the line 1. In this way, the first character data CHR ₂₁ to CHR ₇₁ of the data buffers DB # ₂ to DB # ₇ corresponding to lines 2 to 7, respectively, are
Shift register SFR ₂ to 7 corresponding to the lines 2 to 7
Transfer and store in SFR ₇ .

Note that each shift register SFR ₀ to SFR ₇ has 10 memory cells, and 8 memory cells corresponding to the above lines.
Bit character data is from cell 2 to cell 9.
It is assumed that the first cell stores a start bit and the tenth cell stores a stop bit.

CLK in the data sending unit DSU is
A clock generation circuit that synchronizes with the data sent to
CNT is a counter, and the above clock generation circuit
CLK, and in this case, every time a clock is counted, the count value is sent to the selection line SEL, and the value is used to sequentially specify shift registers SFR ₀ to SFR ₇ to select the specified shift register. - Send the data (bits) stored in the rightmost cell of the register to the transmission line L via the multiplexer MPX.

When the counter CNT counts eight clocks, the count value returns to "0" and an overflow signal is generated. The overflow signal causes the shift instruction SFT to be sent to each shift register.
SFR ₀ to SFR ₇ and the corresponding shift register
The contents of SFR ₀ to SFR ₇ are shifted to the right by one cell. And this time shift register SFR ₀ ~ SFR ₇
The contents shifted to the rightmost cell are time-division multiplexed again in the same manner as above and sent to the transmission line L.

Repeating the above operation, the system register
The contents of SFR ₀ to _{SFR 7} are sent to the data receiving section of the other party.

The above transmission is completed and the shift register SFR ₀
~ When the contents of SFR ₁ become empty, the second character data CHR ₀₂ stored in each of the data buffers DB # ₀ to DB # ₇ of the memory MEM,
CHR ₁₂ to CHR ₇₂ are sent in the same manner as described above, and in this way, the contents of data buffers DB# ₀ to DB# ₇ are sent to the other party.

As shown in Figure 4, in the multiplex data transmission system according to the conventional technology, shift registers are provided for each line, so the scale of the equipment (circuit) increases in proportion to the number of lines, and the cost is also simply proportional to the scale of the equipment. There is a tendency to increase.

In addition, the shift register SFR ₀ ~
When configuring SFR ₇ , if you use an IC configured as a 4-bit shift register, which is generally easily available, 3 ICs are required for one register.
In total, 24 ICs are required.

In addition, in this type of system, a processor (Fig. 1,
In many cases, the processor is controlled using an MPU (MPU in FIGS. 3 and 4), but in many cases the processor's ability cannot be fully utilized, and there is often some leeway left.

Purpose of the Invention The present invention eliminates the above-mentioned drawbacks of the prior art in the multiplex data transmission system as described above, utilizes the spare capacity of the processor, simplifies the circuit configuration of the multiplex data transmission system, and reduces the required IC. The aim is to provide a cheaper device by reducing the number of devices.

Examples of the invention Embodiments of the present invention will be described below with reference to the drawings.

FIG. 5 is a connection diagram of an embodiment of the present invention. In the figure, DSU is a data sending unit, L is a transmission line,
As in FIGS. 1 and 4, MPU represents a processor, MEM represents a memory, and PRB represents a processor bus. In this embodiment, like the one shown in FIG. 4, eight 8-bit data (eight lines) are time-division multiplexed and transmitted.

The data sending unit DSU has a first-in register having a capacity of 10 bits x 8 words instead of the eight 10-bit shift registers SFR ₀ to SFR ₇ shown in FIG.
It uses a first-out memory FIFO and includes a clock generation circuit CLK and a counter CNT synchronized with the transmission line L similar to that shown in FIG. 4, and also includes a control circuit CTL for sending a shift-in instruction. First-in-first-out memory FIFO, as is well known, is a memory in which data is read in the order in which it is written.

The memory MEM has lines 0 to 7 as in Figure 4.
(Not shown) Supported data buffer DB# ₀ ~ DB
# ₇ is set, but in addition to this, an 8-bit assembly buffer ASMB is also set.

Data representing characters of 8-bit codes sent from lines 0 to 7 are stored in data buffers DB# ₀ to DB# ₇ corresponding to the lines, respectively.

To send the data (characters) of data buffers DB# ₀ to DB# ₇ using asynchronous synchronization, first,
Memory MEM assembly buffer ASMB
Each bit position #0, #1, #2 of (#0 to #7),
. . . #7 are set to "0" as start bits ST ₀ to ST ₇ . It is then read and transferred to the first-in, first-out memory FIFO via the processor bus PRB. Data on lines 0 to 7 are assembled into one word by setting #0, #1, #2 to #7 in the corresponding bit positions of the assembly buffer ASMB in the order of lines 0 → 7, and are first processed in parallel.・Control circuit CTL transferred to and input to the in-first-out memory FIFO and controlled by the processor MPU
According to the shift-in instruction SFI output from , it is shifted to the right end. At this time, the data at bit position #0 of the assembly buffer ASMB is placed in the top column (word) of the first-in-first-out memory FIFO, the data #2 is placed in the second column, etc. Data (bits) from 0 to #7 are stored sequentially down the columns (words) of the first-in, first-out memory FIFO. Start bits ST ₀ -ST ₇ are stored as described above.

Next, the data buffers corresponding to lines 0 to 7 are
The bit information in the first bit position of each of the first character data CHR ₀₁ , CHR ₁₁ to CHR ₇₁ of each of DB# ₀ to DB# ₇ is transferred to the bit position #0 to bit position of the assembly buffer ASMB in line order.
Sequentially write to #7 to assemble the word to be transferred to the first-in, first-out memory FIFO.

This word assembled in the assembly buffer ASMB is transferred and inputted to the first-in-first-out memory FIFO in the same way as the start bit, and is inputted first by the shift-in instruction SFI from the control circuit CTL. The data is stored in the bit position (second bit position) next to the data (start bits _ST0 to _ST7 ) stored in the first bit.

Repeat the above process, that is, read the bits at the corresponding bit positions of each data in the order of the bit positions of the data in the data buffers DB# ₀ to DB# ₇ corresponding to each line in the order of the lines, and every circuit round. Assemble one word in the assembly buffer ASMB,
By sequentially transferring and storing the words in the first-in, first-out memory, the first-in, first-out
The memory FIFO is filled with data (characters represented by 8 bits) sent from lines 0-7. At this time, data corresponding to lines 0 to 7 is stored in the 0th, 1st, . . . , 7th columns (words) of the first-in-first-out memory FIFO, respectively.

Transmission line L generated from clock generation circuit CLK
Counter CNT counts the clocks synchronized with
Control multiplexer MPX with counting results to create first-in first-out memory
Read out the cells on the output side of the FIFO sequentially from the top,
It is time-division multiplexed into bit serial data and sent to transmission line L. When all the contents of the cells on the output side are read out, the counter CNT is
A shift instruction SFT is sent from
The contents in the in-first-out memory FIFO are shifted one bit to the right, and the data bit to be sent out and indicated on the transmission line L is then stored in the cell on the output side.

When the above operation is repeated and the contents of the first-in first-out memory FIFO are sent out, the first-in first-out
Data buffers DB# ₀ to DB# ₇ corresponding to lines 0 to 7 are placed in the empty space at the left end of the out memory FIFO.
The second character data of CHR ₀₂ , CHR ₁₂
~CHR ₇₂ is subjected to the same processing as described above, and the data of these characters are continuously sent to the transmission line L as bit serial time division multiplexed data.

In the present invention, when data bits are read from the first-in-first-out memory FIFO and sent to the transmission line L, the data bits are operated in synchronization with the transmission line clock.
The operations of assembling words in the ASMB and transferring and storing the assembled words in the first-in, first-out memory FIFO are performed by the processor MPU.
The control is performed asynchronously and in parallel with the transmission line clock.

In the present invention, an assembly buffer ASMB is provided in the memory MEM, and a first-in first-out memory is provided here.
Assemble the data to be transferred and input to FIFO,
This will increase the load on the processor MPU, but in general, in this type of data sending device, the processor often has a margin of capacity, and by utilizing this margin, processing can be carried out within the capacity of the processor MPU. can be done,
There is no particular need to add a processor.

Although one embodiment of the present invention has been described above,
The present invention is not limited to the above embodiments, and various modifications can be made within the technical scope thereof.

Effects of the Invention Since the present invention is configured as described above, in the multiplex data transmission method as described above, the installation of a shift register corresponding to the conventional line is abolished, and the storage capacity sufficient to cover the necessary lines is provided. have 1
By using first-in, first-out memory configured as LSIs,
This has the effect of reducing the number of ICs and making this type of multiplexed data transmission method more economical. Note that the use of first-in, first-out memory increases the load on the processor, but in this type of multiplexed data transmission method, the load on the processor is not so large;
Processors usually have extra capacity, so by making use of this extra capacity, there is no need to add more processors, and it is thought that the cost will not increase.

[Brief explanation of drawings]

Figure 1 is a block diagram showing an overview of the multiplexed data transmission system, Figure 2 is an explanatory diagram of the asynchronous transmission system for 8-bit data, and Figure 3 shows how data representing the characters of multiple lines is transmitted in bit serial format. Figure 4 is a diagram explaining the principle of division multiplexing and transmission method.
Bit data representing the characters of multiple lines
FIG. 5 is a diagram illustrating the configuration of an example of a conventional method for serially time-division multiplexing and transmitting data. FIG. DSU...Data transmission unit, L...Transmission line, MPU
...Processor, MEM...Memory, PRB...Processor bus, MPX...Multiplexer,
DMPX...Demultiplexer, CLK...Clock generation circuit, CNT...Counter, DB# ₀ to DB
# ₇ ...Data buffer, ASMB...Assembly buffer, FIFO...First-in first-out memory.

Claims (1)

[Claims] 1. In a multiplex data transmission method in which data from multiple lines is serially transmitted in a bit-multiplexed manner over one transmission line, a processor that operates asynchronously with the transmission line clock, a memory, a first-in-first-out memory, and the first ·in·
Data transmission using a single transmission line that includes a counter for operating the first-out memory in synchronization with the transmission line clock and transmits the contents of the first-in first-out memory as multiplexed data. The memory has a data buffer corresponding to each of the plurality of lines, and the processor stores the bits at the corresponding positions in the order of the bit positions of the data in the data buffer corresponding to each line. Read in this order,
One word is assembled for each round of the line, and the word is sequentially transferred to and stored in the first-in-first-out memory, while a counter is operated in synchronization with the transmission line clock. Multiplexed data transmission characterized in that multiple bit parallel outputs based on the above stored contents of the first-in-first-out memory are selected by the value of the counter and sequentially sent to the one transmission path. method.