JPH0153540B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a speed converting device, and particularly to a speed converting device for main scanning speed in a facsimile receiving device.

Generally, a speed conversion device of a facsimile receiving device converts a written image signal having a main scanning speed that is repeated in a first period into a writing address generated in response to a writing start pulse having the first period. The memory circuits alternately write to a pair of memory circuits, each storing pixels for at least one scanning line, and respond to a read address generated in response to a read start pulse having a second cycle shorter than the first cycle. The speed-converted recorded signals are obtained by reading the signals alternately.

A conventional example of a speed conversion device will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing a conventional example.

A conventional example described below includes a pair of memory circuits M1 and M2, a write address generation circuit 2, a read address generation circuit 4, and a sub-scanning control circuit 8.

Next, the operation of the conventional example shown in FIG. 1 will be explained with reference to the schematic perspective view of the recording section in FIG. 1 shown in FIG. 2 and the time chart in FIG. 1 shown in FIG. 3. In the following explanation, the first period T1 is 1.2 times the second period T2.

The recording section 9 includes a laser light source 2 as shown in FIG.
The laser beam from 1 is optically modulated by an optical modulator 22 and enters a rotating reflecting mirror 23 . The rotating reflector 23 is 1
It has two mirror surfaces and is fixed to a shaft connected to the rotating shaft of the synchronous motor 24. The synchronous motor 24 is synchronously controlled by a synchronous clock from the synchronous clock generating circuit 7 (not shown) to rotate synchronously, and rotates the rotary reflector 23 clockwise at a second synchronization T2.

The reflected light from the rotating reflector 23 is passed through the Fθ lens 25
After that, the light is focused on the roll-shaped photosensitive recording medium 26, and main scanning is performed on the photosensitive recording medium 26 from right to left as shown by the dotted line L in FIG. 2 to perform exposure recording.
At the start point of this main scan, when the laser beam irradiates the photodetector 30, the photodetector 30 generates a scan start pulse g.

On the other hand, when the sub-scanning control signal h is supplied to the pulse motor 27, the pulse motor 27 rotates by a predetermined angle, and the rotation of the pulse motor 27 rotates the paper feed roller 29 via the belt 28, and the photosensitive recording medium 2 is moved by one scanning line in the direction of arrow F to perform sub-scanning.

A writing signal a having a main scanning speed that is repeated at a first cycle T1 transmitted from the transmitting side is supplied to a writing start pulse generation circuit 1, and the writing start pulse generating circuit 1 generates an image for each scanning line of the writing signal a. signal a
1, a2, a3, . . . is detected and outputted as a write start pulse b having a pulse duration p. Therefore, the cycle of the write start pulse b is the first cycle T1. Further, the pulse time width p is set to a time corresponding to several pixels.

The write address generation circuit 2 includes a counter and a flip-flop, and the counter is activated at the falling edge of the supplied write start pulse b, and the clock s is activated.
A write address is generated using 1 as a clock.

Next, time t1 of the time chart shown in FIG.
, the counter of the write address generation circuit 2 specifies the memory circuit M1 for writing. on the other hand,
The drawing signal a transmitted from the transmitting side is supplied to the analog-to-digital conversion circuit 5, where it is converted into a digital signal and supplied to the storage circuits M1 and M2.

Therefore, the image signal a1 for the first scanning line of the image signal a is written into the memory circuit M1 in response to the write address generated in response to the write start pulse b1. When the writing of the image signal a1 is completed, the flip-flop operates to reset the counter to zero and switch the counter to the memory circuit M2.

Here, if the number of pixels per scanning line is "N", then the capacity of each of the counter of the write address generation circuit 2 and the memory circuits M1 and M2 is "n×
N'' (an integer of n1) bits. Therefore, by setting the first period T1, the period of the clock s1 is determined.

On the other hand, the scanning start pulse g generated from the recording section 9 described above is supplied to the readout start pulse generation circuit 3, and the readout start pulse generation circuit 3
A read start pulse c having a pulse time width p' of 2 is generated. The pulse time width p' is set under the same conditions as the pulse time width p described above.

The read address generation circuit 4 includes a counter, a flip-flop, and an exclusive OR circuit.
The read address generation circuit 4 compares the memory circuit whose write address specifies writing with the memory circuit whose read address specifies read using an exclusive OR circuit, and when the two memory circuits do not match, that is, the read timing. When the old storage circuit is not in the process of writing, a counter is activated at the fall of the read start pulse c and a read address is generated using the clock s2 as the clock.

When the reading is completed, the flip-flop operates to return the counter to zero, generate a read end pulse d, and switch the counter to the next storage circuit.

Here, clock s2 is “s2=T2/n・N”
(However, n1 is an integer).

The sub-scanning control circuit 8 generates a sub-scanning control signal h when the read end pulse d is supplied, rotates the step motor 27 of the recording section 9 shown in FIG. Move in the direction of arrow F.

At time t1 in FIG. 3, a read start pulse c1 is generated, but since the counter of the read address generation circuit 4 specifies the memory circuit M1 and the memory circuit M1 is being written, no read address is generated. Subsequently, a read start pulse c2 is generated at time t2, but a read address is not generated because the memory circuit M1 is still being written.

Writing to the memory circuit M1 is completed immediately before time t3, and the counter of the write address generation circuit 2 returns to zero and specifies the memory circuit M2. time t
3, a write start pulse b2 is generated and supplied to the write address generation circuit 2, which generates a write address and starts writing the image signal a2 for the second scanning line of the image signal a into the memory circuit M2.

Next, at time t4, readout start pulse c
3 is generated and supplied to the read address generation circuit 4, which generates a read address and reads out the image signal a1 written in the memory circuit M1.The read digital signal is converted into an analog signal by the digital-to-analog conversion circuit 6. It is output as a recorded image signal e1' in the recorded signal e'.

The recorded image signal e1' is supplied to the optical modulator 22 of the recording section 9 shown in FIG. 2, and the optical modulator 22 is operated.

At time t5, a read start pulse b3 is generated and writing to the memory circuit M1 is started from time (t5+p). At this point, the memory circuit M1
is being read, and the read address generation circuit 4
The logical sum of the exclusive OR circuits is calculated, and the counter of the read address generating circuit 4 stops and returns to zero. Therefore, reading of the memory circuit M1 takes time (t5
+p) and subsequent steps are not performed, and a recorded image signal e1' is obtained in which the signal is omitted compared to the image signal a1.

When the counter of the read address generation circuit 4 returns to zero, the counter is switched to the memory circuit M2, and when the read end pulse d1 is generated, sub-scanning for one scanning line is performed.

That is, the conventional speed converting device has a drawback that when the writing timing of the memory circuit that is being read comes, the writing/picture signal generated after that in the scanning line is dropped, degrading the image quality.

An object of the present invention is to eliminate the above-mentioned drawbacks, to operate a memory circuit such that the timing of writing and reading is always repeated alternately, to respond to address instructions for writing and reading, and to perform writing and reading to each address at respective timings. To provide a speed conversion device capable of improving image quality by preventing dropout of writing signals for each scanning line by continuing reading when the memory circuit during reading reaches the writing timing. .

The speed conversion device of the present invention includes a storage circuit that is divided into two sections and has a capacity to store pixels for at least two scanning lines, and a document signal having a main scanning speed that is repeated in a transmitted first period. a write address generation circuit that generates a write address in response to a write start pulse having the same period as the write address, and specifies a section of the memory circuit to be written next in response to the end of generation of the write address for each scanning line; generating a read address in response to a read start pulse of a second period shorter than the first period when a section of the storage circuit designated for reading is not being written; and terminating the generation of the read address for each scanning line. a read address generation circuit that designates the section of the memory circuit to be read next in response to the above and generates a read end pulse; and a timing pulse generation circuit that generates a write timing pulse and a read timing pulse, and in response to the write timing pulse and the read timing pulse, generates a memory circuit designated by the write address and the read address, respectively. The configuration is such that the writing and drawing signals are written to and read from each address.

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 4 is a block diagram showing one embodiment of the present invention.

One embodiment of the present invention includes a pair of memory circuits M1, M
2, a write address generation circuit 2, a read address generation circuit 4, a sub-scanning control circuit 8, and a timing pulse generation circuit 10.

Next, the operation of the embodiment shown in FIG. 4 will be explained with reference to the time chart in FIG. 4 shown in FIG. In the following explanation, the processes for obtaining the drawing signal a, the write start pulse b, the read start pulse c, the read end pulse d, and the scan start pulse g are the same as those in the conventional example described above. Further, the operation of the sub-scanning control circuit 8 is the same as that of the conventional example described above, and a complete explanation thereof will be omitted. Note that the first period T1 is equal to the second period T2.
Let's explain the case where there is a 1.2x relationship.

The timing pulse generation circuit 10 includes two sets of counters, and generates a write timing pulse w and a read timing pulse r from clocks s1, s2, and s3 supplied from the synchronous clock generation circuit 7'. That is, as shown in the time chart for explaining the operation of the timing pulse generation circuit 10 in FIG. 4 of FIG.
1, s2, and s3 are set in the relationship "s3>s2>s1". In the example, “s3=2s2=2×4×1.2s1”
It is set to .

The write timing pulse w is a "low" potential pulse that occurs at the next falling edge of the clock s3 after every rising edge of the writing clock s1, and disappears at the rising edge of the clock s3, and the read timing pulse r occurs at the rising edge of the reading clock s2. This is a "high" potential pulse that occurs at the rising edge of the next clock s3 and disappears at the falling edge.

The write timing pulse w and the read timing pulse r are supplied to the switching circuit 11. The switching circuit 11 responds to the write timing pulse w and the read timing pulse r to issue write and read instructions to respective addresses of the memory circuit designated by the write address and the read address, respectively. Therefore, writing and reading to and from the same memory circuit becomes possible.

In the time chart shown in FIG. 5, the time t
The operations of writing to the memory circuits M1 and M2 and reading from the memory circuit M1 from time t4 to time t4 are the same as those of the conventional example described above, and the explanation thereof will be omitted.

At time t5, write start pulse b3 in write start pulse b is generated, and at time (t5+
In p), the memory circuit M1 starts writing the image signal a3 to the third scanning line in the drawing signal a.

At time (t5+p), the memory circuit M1 is in the process of reading, but because of the time division of address writing and reading using the write timing pulse w and read timing pulse r mentioned above, writing and reading from the same memory circuit M1 continues. be able to.

Note that if reading is started first because "T1>T2", the write address will not catch up with the read address, so the read from the memory circuit M1 will be completed.

Therefore, the recorded image signal e1 in the recorded signal e obtained by analog-converting the read signal by the digital-to-analog conversion circuit 6 is such that the image signal a1 corresponding to the first scanning line in the document and image signal a has no signal dropout. The signal is obtained as a speed-converted signal.

When reading from the memory circuit M1 is completed, the flip-flop of the read address generating circuit 4 operates to stop the counter and return it to zero, and then switches the counter to the memory circuit M2 to generate a read end pulse d1 in the read end pulse d. The read end pulse d1 is supplied to the sub-scanning control circuit 8,
Sub-scanning for one scanning line is performed.

By repeating writing and reading in this way, the transmitted calligraphic signal a having the first period T1 is converted into the speed-converted recording signal e having the second period T2 shorter than the first period T1. Can be converted.

As explained above, in the embodiment of the speed conversion device according to the present invention, the first period T1 is changed to the second period T.
However, this is just one example; as long as the first period T1 is larger than the second period T2, the object of the present invention can be achieved in any case. Further, in the embodiment, a facsimile receiving device using a rotating reflecting mirror is used, but the present invention can also be applied to a facsimile receiving device using a rotating polygon mirror and a cylindrical scanning type facsimile receiving device.

Furthermore, although a laser light source was used as the recording element and a photosensitive recording medium was used as the recording medium, a glow discharge tube may also be used as the recording element. Furthermore, the same effect can be obtained by applying the present invention by using a thermal recording head when thermal recording paper is used as the recording medium, and an electrostatic recording head when electrostatic recording paper is used as the recording medium. It will be done.

In the embodiment, the writing signal is converted to digital and stored, and the read digital signal is converted to analog to obtain the recording signal, but by using CCD type analog memory etc. without performing such conversion, the analog There is no problem in handling it as a signal.

Further, although one pair of memory circuits is used, any memory circuit may be used as long as it is divided into two sections and has a capacity capable of storing pixels for at least two scanning lines.

Furthermore, the first generation timing of the readout start pulse may be any time within the range of the first period, and neither is intended to limit the scope of the present invention.

As described above, the speed conversion device of the present invention adds a timing pulse generation circuit, and when the memory circuit being read reaches the write timing, instead of discarding the subsequent calligraphy/picture signal written in the memory circuit. , the memory circuit is operated so that the timing of writing and reading is always repeated alternately, and in response to address instructions for writing and reading, writing and reading to each address are performed at respective timings, and By continuing reading when the memory circuit reaches the write timing, there is an effect that the image quality can be improved by preventing dropout of the writing signal for each scanning line.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing a conventional example, Fig. 2 is a schematic perspective view of the recording section in the conventional example shown in Fig. 1, and Fig. 3 is a timing chart for explaining the operation of the conventional example shown in Fig. 1. 4 is a block diagram showing one embodiment of the present invention, FIG. 5 is a time chart for explaining the operation of the embodiment shown in FIG. 4, and FIG. 6 is a block diagram showing the operation of the embodiment shown in FIG. This is a time chart for explaining the operation of the timing pulse generation circuit. In the figure, 1...Write start pulse generation circuit, 2...Write address generation circuit, 3...Read start pulse generation circuit, 4...Read address generation circuit, 5...Analog-to-digital conversion circuit, 6...
...Digital-to-analog conversion circuit, 7, 7'...Synchronous clock generation circuit, 8...Sub-scanning control circuit, 9...
... Recording section, 10 ... Timing pulse generation circuit,
11...Switching circuit, a...Document/image signal, b...Writing start pulse, c...Reading start pulse, d...
Read end pulse, e...recording signal, g...scanning start pulse, h...sub-scanning control signal.

Claims (1)

[Claims] 1 A memory circuit that is divided into two sections and has a capacity to store pixels for at least two scanning lines, and a write start pulse that has the same cycle as the writing signal that has the main scanning speed that is repeated at the first transmitted cycle. a write address generation circuit that generates a write address in response to the write address and specifies a section of the memory circuit to be written next in response to completion of generation of the write address for each scanning line; and the memory circuit designated for reading. When the segment is not being written, a read address is generated in response to a read start pulse of a second period shorter than the first period, and the next read is performed in response to the end of generation of the read address for each scanning line. a read address generation circuit that specifies a section of the storage circuit to be read and generates a read end pulse;
a timing pulse generation circuit that generates a write timing pulse and a read timing pulse by time-sharing the write and read timings so as to correspond to the respective occurrences of the write and read addresses; A speed converting device characterized in that, in response to a pulse, the writing/image signal is written to and read from each address of the storage circuit designated by the writing address and the reading address, respectively.