JPH0155783B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a method for controlling logic signals between chips on the same card equipped with Josephson circuits such as Josephson logic circuits and memory circuits, or between cards equipped with such chips, in Josephson computer components. Concerning transmission systems, normal and stable operation is possible by reducing the noise current caused by crosstalk in the signal transmission system caused by the power supply current that drives various circuits or the high-frequency current required to create synchronization signals for calculation processing. The invention relates to Josephson receiver circuits.

In recent years, progress has been made in the application of Josephson devices that operate at extremely low temperatures to digital devices. The Josephson device has an extremely high switching speed of several tens of psec, and the amount of heat generated per gate is several μw to several tens of μw, which is two to three orders of magnitude smaller than conventional silicon devices. Because of this high speed and low power consumption, high-density packaging is possible, and it has the potential to create high-performance, ultra-high-speed computers. An example of computer implementation is shown in Figure 1. Josephson circuits such as logic circuits and memory circuits are formed on the chip 1. The chips are mounted on the card 2 by flip-flop bonding as shown in FIG. 2, and electrical contact is made through contacts 5. 1a is wiring on the chip, 2a is wiring on the card, and 1b and 2b are superconductor grounds. A device is constructed by attaching a plurality of cards 2 to a board 3, and electrical contact between the cards 2 and the wiring board 4 is made by a micro connector 6 shown in FIG.
This is done through Wiring from the contact point 5 on the chip to the contact point 5 on the card, wiring from the line point 5 on the card to the micro connector 6, wiring from the contact point 5 on the card to the contact point 5 on the same card's separate chip, and wiring on the wiring board 4,
The wiring from the micro connector 6 to the micro connector on the board 4 corresponding to another card is constructed by forming a strip line consisting of a superconductor ground and superconductor wiring on the chip card 1 and the wiring board 4. When using the output of a Josephson circuit mounted on one chip to operate a Josephson circuit mounted on a chip on the same card or on a different chip, a high-speed signal output current with an extremely small rise time of several tens of ps is required. It must be transmitted to the input of the Josefson circuit to be operated. Here, the Josephson circuit that outputs the output is a final stage gate circuit of a Josephson circuit such as a normal logic circuit or a memory circuit, or a Josephson driver circuit specially designed for signal input. A Josephson receiver circuit is a gate circuit that generates an output corresponding to the high-speed signal input transmitted between the same card chips and between different card chips.
Here, we will discuss in more detail the transmission system through which signals are transmitted. First, regarding the signal transmission system between chips of the same card, [Josephson circuit or Josephson driver circuit → On-chip wiring →
Contact → Wiring on card → Contact → Wiring on chip → Josephson receiver circuit]. The signal transmission system between different card chips is as follows: Josephson circuit → driver circuit → wiring on the chip → contacts → wiring on the card → micro connector → wiring on the wiring board → micro connector → wiring on the card → contacts → wiring on the chip →
Josephson receiver circuit]. On the other hand, the power supply circuit that generates the bias current to drive the Josephson circuit is constructed on a chip. The Josephson circuit has the characteristic (latching mode) that once it is in a state where it outputs a signal, it continues to do so until the bias current is returned to zero.
In the power supply circuits proposed to date, a state in which the bias current periodically becomes zero cannot be created unless a high-frequency current is applied to the input. Therefore, it is necessary to supply high frequency current from room temperature to the on-chip power supply circuit. The power supply system is also [wiring on the wiring board → micro connector → wiring on the card → contacts → wiring on the chip → power supply circuit], and when a high frequency current flows through the power supply system, the signal transmission system between the chips and the signal transmission between the cards are connected. It connects capacitively and inductively to the signal transmission system and generates a crosstalk current on the signal transmission system. This crosstalk current propagates in the direction of the Josephson receiver circuit, but
If this value exceeds the threshold of the receiver circuit, the receiver circuit will produce an output even though no signals from other chips are input. In other words, this will cause an error difference.

For example, the circuit shown in Figure 4 is based on IBM's M.
Klein proposed [“chip-to-chip Driver and
Receiver Circuits for a Josephson
Computer”, IEEE J. of Solid-State Circuits,
SC-17(4)pp739-743] Receiver circuit. High-speed signal I ₁ transmitted through wiring 9 (long line)
is input to the gate Q ₁ of the receiver circuit, causes a voltage transition in this gate Q ₁ , inputs an output current to the gate Q ₂ , causes a voltage transition in Q ₂ , and supplies the output current I _L of the next stage circuit. When the signal I _I is zero, the output current I _L is also zero. Figures 5a and 5b show the circuit configuration and threshold characteristics of the gate _Q1 that support the input current I _I and output current I _L characteristics of this receiver circuit, respectively.
Here, L ₁ = 7.3PH, L ₂ = 1.5PH, L ₀₁ = 0.05mA,
I ₀₂ =0.25mA. Bias current of gate Q ₁
For example, if IB is 0.2mA, the threshold value is
It becomes 0.05mA. Since the signal level is about 0.2 mA, when the signal I _I is input, the gate Q ₁ switches and supplies the output current I _L to the next stage gate. When the signal I _I is not input, the gate Q ₁ does not switch and no output current I _L is generated, but a value of 0.05 mA or more is input to the gate Q ₁ due to the power supply current crosstalk noise current mentioned above. Then, the gate _Q1 switches, producing an output current I _L. That is, the output current I _L even though there is no signal I _I
This causes an error signal to be given to the Josephson circuit at the next stage. This crosstalk noise is caused by magnetic coupling due to mutual inductance between the micro connectors 6 and the contacts 5, and it is difficult to reduce it to 0.05 mA or less due to mounting design.
becomes an important issue.

In order to eliminate these drawbacks, the present invention provides a Josephson receiver circuit in which the magnetic field due to the noise current input to the Josephson quantum interference device is extremely reduced to ensure normal operation.

The present invention will be explained in detail below with reference to the drawings.

FIG. 6 shows an embodiment of the present invention, and 7 is an input current.
This is a magnetically coupled Josephson quantum interference device that can control the output current I _L by the magnetic field generated by I _I.
A two-junction SQUID [Super-Conducting
A wide range of quantum interference devices such as Quantum Interference Device (superconducting quantum interference device) and 3-junction SQUID can be used. 8 is a first inductance connected to a signal transmission line (long line) 9, and 10 is a first mutual inductance that provides magnetic input to the quantum interference device 7. A delay circuit 11 is a passive circuit having a delay time D longer than the rise time of the signal _II , and is continuously connected to the first inductance 8. A second inductance 12 is connected in series to this delay circuit 11, and is magnetically coupled to the quantum interference device 7 through a second mutual inductance 13. The magnetic coupling directions of the first mutual inductance 10 and the second mutual inductance 13 are opposite.
That is, for example, when a direct current is applied from the long line 9, the first mutual inductance 10
The magnetic inputs given to the quantum interference device by the second mutual inductance 13 and the second mutual inductance 13 are configured to have opposite polarities and become zero. Reference numeral 14 denotes a terminating resistor of the signal transmission system, and its resistance value is usually the same as the characteristic impedance of the long line 9.

Here, it is assumed that high-frequency noise with an amplitude I _N and an angular frequency ω is propagated from the left side of the long line 9 toward the receiver input, that is, toward the first inductance 8 as crosstalk noise due to the power supply current. The noise current flowing through the first inductance 8 can be expressed as I ₁ =I _N sinωt. When this noise current passes through the delay circuit 11 and flows into the second inductance 12, this current flows through the second inductance 12 from right to left and can be expressed as in the following equation.

I ₂ =I _N sinω(t-D) (1) Here, D is the delay time of the delay circuit 11.
Therefore, the magnetic field applied to the quantum interference device 7 is Φ=M ₁ I ₁ −M ₂ I ₂ =M ₁ I _N sinωt−M ₂ I _N sinω(
t-D)...(2). Here, M ₁ and M ₂ are the values of the first and second mutual inductances 10 and 13, respectively.
Usually, M ₁ = M ₂ = M, so equation (2) is Φ = MI _N {sinωt−sinω(t−D)}=2MI _N sinω/2D
cosω(t-D/2)...(3). This amplitude value is _2MIN sinω/2D.

On the other hand, in the normal receiver circuit described as the prior art, this cancel effect does not exist, and the amplitude of the magnetic field due to the noise current applied to the quantum interference device 7 is Φ _N = _MIN (4). Here, a cancel parameter P is used as a parameter indicating the noise current reduction effect according to the present invention.
can be defined and given as the noise magnetic flux ratio by the following equation.

P=Φ/Φ _N =2MI _N sin(ω/2D)/MI _N =2 sin(ω/
2D)
...(5) Here, to find the value of P specifically, ω is the angular frequency of the high-frequency power supply current. This power supply current will also be used as the synchronous machine clock of the computer; for example, if the machine clock is 5ns
Assuming that, the power supply frequency will be 100MHz,
ω=2π=2π・100MHz. Next, regarding the delay time D of the delay circuit, this value is equal to the signal I _I
With the input, the quantum interference device must produce an output, which must be greater than the rise time tr of the signal I _I. Normally, the rise time tr of the Josefson signal is 20 to 30 ps, and even if this signal is subjected to waveform distortion due to band limitations in the transmission system, the rise time of the signal _II immediately before input to the receiver is 70 to 30 ps. It is thought to be 80ps. Therefore, D should be designed to be about 100 ps.
Substituting the values of ω and D into equation (5) to find P, P becomes approximately 6 × 10 ^-2 , which can be reduced to less than 6% of the actual noise current. The probability of circuit malfunction can be reduced.

Figure 8 shows three junctions as a quantum interference device 7.
This is a Josephson receiver circuit using SQUID, and the values of the first and second inductances are 8 and 11.
16PH, first and second mutual inductance value 13
PH, one Josephson critical current value I ₀ 0.113
mA, and the delay circuit delay time D is 100 ps.

FIG. 9 shows the threshold characteristics of this receiver circuit. Here, for example, if the bias current value of the receiver circuit is set to 0.2 mA, the corresponding threshold level will be 0.13 mA. Signal I _I
(level approximately 0.2 mA), the receiver generates an output current I _L and operates normally. The noise amplitude value I _N that causes malfunction due to noise current is 0.13 m.
It can be obtained by dividing A by P, and I _N is
It becomes 2.2mA. This circuit is extremely resistant to power supply current crosstalk noise, and has excellent allowable noise characteristics that are 44 times higher than the long line receiver circuit proposed by M.Kiein mentioned in the conventional technology section. have

Next, the following three types of configurations of the delay circuit 11 will be shown. First, the simplest configuration uses a superconducting strip line, which is the same as the long line. This has the feature that it is possible to form a delay circuit with the same characteristic impedance as that of a long line. The disadvantage is that the amount of delay per unit length is small and the delay circuit becomes large.
FIG. 10 shows an example of a cross-sectional view of a long line 9 used as wiring for chips, cards, wiring boards, etc. Here, 15 is a superconducting ground plane, 16 is a first insulating layer, 17 is a second insulating layer, and 18 is a wiring. The delay time per unit length of this long line is 80 to 90 ps/cm,
To configure a delay circuit with a delay time D of 100 ps, its length is 1.3 cm.

The other two delay circuit configurations achieve high density delay circuits. One is to configure a delay circuit using a stripline having a high dielectric constant and an insulating layer. The basic structure is the same as that shown in FIG. As the insulating layer, Nb ₂ O ₅ , TlCl, TiO ₂ , SrTiO ₃ , BaTiO _{3 ,} etc., which have a relatively high electric constant, are used. In particular, Nb ₂ O ₅ can be easily formed by anodizing Nb, which is usually used as a ground plane for Josephson circuits and strip lines. A drawing in the case of using Nb oxide is shown in FIG. 11. In this case, the delay time per unit length can be 500 ps/cm or more, and the stripline length as a delay circuit can be 2 cm or less.

Another configuration is one consisting of passive elements of lumped constant inductance L and lumped constant capacitance C shown in FIG. C at both ends of L
is connected to ground. A delay circuit is constructed by connecting several to several tens of these π-type circuits in series. The delay of one π-type filter is given as √, and if the number of series connections is N, then
The delay time D of the entire delay circuit is given as N√. It is useful to construct the lumped constant inductance L by a stripline on a ground plane hole, which can increase the inductance value per unit length. This is shown in FIG. Here, 19 is a superconducting ground plane,
20 is a ground plane hole, and 21 is a wiring.

As explained above, since the present invention has characteristics that are extremely resistant to crosstalk noise caused by power supply current,
This has the advantage of increasing computer packaging density and making it possible to use an increased power supply current supplied from an external source.

[Brief explanation of drawings]

Figure 1 is a block diagram of an example of a computer mounting method, Figure 2 is an enlarged cross-sectional view of the chip bonding part in Figure 1,
Figure 3 is an enlarged sectional view of a micro connector connected to a card and wiring board, Figure 4 is a circuit diagram of a conventional Josephson receiver circuit, and Figures 5a and b are the circuits of gate _Q2 in Figure 4, respectively. Figure and its threshold characteristics,
Figure 6 is a circuit diagram of an embodiment of the present invention, Figures 7a and b
8 is a circuit diagram using a two-junction SQUID and a three-junction SQUID as configuration examples of the quantum interference device of the present invention, FIG. 8 is a specific design circuit example of the Josephson receiver circuit of the present invention, and FIG. Figure 8 is a threshold characteristic diagram of the receiver circuit configured, Figure 10 is a sectional view of an example of a long line configuration used as a delay circuit in wiring on chips, cards, etc., and Figure 11 is a diagram of the delay circuit used in the present invention. Another configuration example diagram, 1st
Figure 2 shows yet another configuration example of the delay circuit used in the present invention, and Figure 13 shows one in which a stripline above the ground plane hole is used as a means of forming the lumped constant inductance L used in Figure 12. FIG. 1...Chip, 2...Card, 3...Board,
4... Wiring board, 5... Contact, 6... Micro connector, 7... Magnetically coupled Josephson quantum interference device, 8... First self-inductance, 9...
Long line, 10...First mutual inductance, 11...Delay circuit, 12...Second self-inductance, 13...Second mutual inductance, 14...Terminal resistor, 15...Superconductor ground plane , 16...first insulating layer, 17...second insulating layer, 18...wiring, 19...superconducting ground plane, 20...ground plane hole, 21...wiring.

Claims (1)

[Claims] 1. A magnetically coupled Josephson quantum interference device, a first self-inductance that applies a magnetic field to the quantum interference device by a current propagating through a long line, and a subsequent connection to the first self-inductance. a delay circuit having a delay larger than the signal rise time of the signal; and a second self-inductance that is connected to the delay circuit and provides the quantum interference device with a magnetic field in the opposite direction to the magnetic field provided by the first self-inductance. Josephson receiver circuit with. 2. The Josephson receiver circuit according to claim 1, wherein the delay circuit is constructed of a line having the same structure as a long line. 3. The Josephson receiver circuit according to claim 1, wherein the delay circuit is constituted by a superconducting strip line whose insulating layer is made of a material with a high dielectric constant. 4. The delay circuit according to claim 1, wherein the delay circuit comprises a series connection of a π-type passive element circuit consisting of a lumped constant inductance L and a lumped capacitance C connected to the ground at both ends thereof. Josefson receiver circuit.