JPH0156475B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory integrated circuit using an insulated gate field effect transistor called an IC memory or MOS memory.

Integrated circuits using insulated gate field effect transistors have been developed into large-scale integrated circuits because they can be easily increased in density. In particular, large-capacity memory integrated circuits have large-capacity memory cells on a common semiconductor substrate, and realize high-performance, highly reliable semiconductor devices. The preferred memory cell for this purpose is a one-transistor random access memory (1TR-
In this type of MOS memory (RAM), transistors for switching and capacitive elements for information storage are arranged at matrix intersections where word lines and digit lines intersect. This 1TR-
In order to prevent the capacitance value of the capacitive element from increasing as the capacity of RAM increases, it becomes necessary to add a highly sensitive sense circuit to the digit line. A preferred conventional circuit technique is to provide transistors operating in saturation on the sense circuit and digit lines.
This circuit technology was also published in the 1975 ISCC Technical Digest Papers ('75ISSCC Technical Digest Papers).
As described by LGHeller et al. in ``Papers'', a sensing operation is initiated by a signal to a sense node that is larger than the signal amplitude of the digit line.

However, in this conventional circuit technology, the precharge state of the digit line before the start of the sense operation controls the conditions at the start of the sense circuit's operation, and since this precharge operation is performed through the transistor in the saturated state, both sides of the sense circuit are It takes a long time to reach the equilibrium precharge obtained at the end of the precharge of the digit line, and the cycle time when performing information read operations one after another is long, and when the cycle time is shortened, the sense node amplitude is improved for reliable information read operations. There is a drawback that you will not be able to obtain

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory integrated circuit with a highly sensitive circuit configuration that provides stability in read operations and short cycle times.

According to this invention, memory cells each having a transistor and a capacitive element are provided at the intersections of a matrix where a plurality of word lines and a plurality of digit lines intersect, and a sense circuit is provided for sensing signals generated on a pair of digit lines. In a memory circuit connected to the pair of digit lines and connected with a precharge circuit that supplies a precharge voltage to the digit lines, turning on a coupling transistor that shorts the pair of digit lines during precharge,
In addition, there is obtained a memory integrated circuit characterized in that the sense circuit is controlled to be inactive, the coupling transistor is turned off after precharging, and the sense circuit is to be activated. The memory integrated circuit obtained here is the so-called 1TR-RAM or
The first and second digit lines are a pair of digit lines, and the first and second digit lines intersect with the word line.
2TR-2C-, in which a switching transistor and a capacitive element are provided for each digit line.
Applies to RAM.

In the memory integrated circuit of the present invention, since the coupling transistor forces the first and second digit lines to be balanced during precharge, a balanced state is obtained before the precharge ends, and a read operation can be started. Therefore, it is possible to shorten the access time to start reading and shorten the cycle time, realizing a high-speed storage device.In addition, as will be described later, the sensitivity caused by reading from another address, which is seen in conventional circuits, can be reduced. There is no instability in operation caused by the drop.

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention.

This embodiment has a memory cell consisting of a transistor and a capacitive element at each intersection of a matrix formed by a plurality of word lines (φ _W , . . . ) and a plurality of digit lines (D, . . . ). For simplicity, this figure only shows one address signal line 11, one dummy address signal line 12, and a digit line D extending on both sides of the sense circuit. The dummy address line 11 is driven by a dummy address signal φd when reading information from a memory cell connected to one digit line D, and transmits information from a dummy cell having a configuration similar to the memory cell to the other digit line.
In other words, the transistor _Q1 of the memory cell has a drain
One of the sources is connected to one digit line D,
The other end is coupled to one end of the capacitive element C, and the gate electrode is driven by the address signal φ _W . Also, one of the drain and source of the dummy cell transistor _Q2 is connected to the other digit line, and the other is connected to the capacitive element.
It is coupled to one end of _C2 , and its gate electrode is driven by a dummy address signal φd. Also, each digit line D,
Transistors Q ₃ and Q ₄ are connected between D and the sense circuit.
are provided, respectively, and transistors Q 3 and Q ₃ are connected to the digit line D and the sense nodes A and B of the sense circuit, respectively.
The output regions called the drain and source of Q ₄ are connected to each other. Transistors Q ₃ and Q ₄ have drive voltages V _R applied to their gate electrodes at sense nodes A and B.
Because it is equal to or lower than the highest potential of
Obtain operation in the saturated state (pentode region). The sense circuit consists of precharge transistors Q ₅ and Q ₆ , sense transistors Q ₇ and Q ₈ , and current drain transistor Q ₉ . The precharge transistors Q ₅ and Q ₆ have their drains connected to the high potential line V _D of the power supply, their sources connected to the sense nodes A and B, respectively, and their gate electrodes driven by the precharge signal φ _L . The sense transistors Q ₇ and Q ₈ have their drains connected to the sense nodes A and B, respectively, their sources commonly connected to the node K, and their gates connected to each other's drains. Also, a current drain transistor
The drain and source of Q ₉ are connected to the node K and the low potential line GND of the power supply, respectively, and the gate electrode is driven by the sense signal φ _S. Furthermore, a coupling transistor is connected to the digit line D extending on both sides of the sense circuit.
The output region of _Q10 is connected, and by driving the coupling signal φ _C to the gate electrode of this transistor, both digit lines are forced to have the same potential during precharging.

Figure 2 shows the operating waveform diagram of the conventional 1TR-RAM. This circuit has output regions connected to sense nodes A and B, respectively. After reading the reverse information of the subsequent address in the preliminary read operation, during the precharge period from t = 0 to t = φ _L , φ _C (OFF), the sense nodes A and B rise to about 6V, and the digit lines D and Precharged to approximately 3V. The voltage conditions here are power supply voltage 8V and drive voltage 5.5V.
All transistors are N-channel insulated gate transistors with a gate threshold of 1V.
At the end of the precharge [t = φ _L , φ _C (off)], the precharge level of the digit line D, which has a large load capacitance, does not reach complete equilibrium, so it is opened when the coupling transistor transitions to the blocking operation. The sense nodes A and B exchange charges with the digit line through transistors operating in a saturated state, changing the potential. Due to the history of reading reverse information at different addresses, the potential of sense node B drops more rapidly than that of one sense node A due to the inflow of electron charge from the digit line. Start of driving address signal [t=
φ _W , φ d (ON)], when the accumulated charges of forward information in the capacitive elements of the memory cells and dummy cells on the digit line D change the potential of the digit line, the sense node A becomes a lower potential than the sense node B, and sensing starts. A differential voltage △V is generated at the time [t=φ _S (ON)]. When the load capacitance of the digit line D is 1.2 pF, and the capacitance values of the memory cell capacitor and dummy cell capacitor are 0.12 pF and 0.06 pF, respectively, this differential voltage is 0.15 V at most. This differential voltage is amplified by driving the sense signal, and precharging is started again from the end of sensing [t=φ _C , φ _L (ON), t=φ _W , φ _d , φ _S (OFF)].

This conventional circuit requires a very long time to completely balance the precharge to digit line D, resulting in slow access times and cycle times for reading stored information. Furthermore, if the precharge time is shortened to shorten this time, the precharge level of the digit line becomes incompletely balanced, resulting in a small differential voltage and an unstable and uncertain information detection operation.

FIG. 3 is a signal waveform diagram of the integrated circuit of the present invention shown in FIG. The precharge signal φ _L is at a high potential of approximately 7V during the precharge period, and the address signal φ _W
And the dummy address signal φ _d becomes a low potential before becoming a high potential. The coupling signal φ _C is an inverse signal of the address signal, and becomes high potential when the address signal φ _W and the dummy address signal are low potential, thereby forcing the digit lines on both sides of the sense circuit to be in a balanced state. Also, the sense signal φ _S is 10 to 30 times smaller than the address signal.
It becomes a high potential with a delay of nanoseconds, and becomes a low potential immediately after the address signal becomes a low potential.

FIG. 4 is an operational waveform diagram of the embodiment of the invention shown in FIGS. 1 and 3. Immediately after the start of precharging (t=0), the digit line D is precharged to the same potential by the arrival of the combined signal, and along with this, the sense nodes A and B are also precharged to the same potential. That is, a precharge operation is already performed in a balanced state during the precharge period, and the influence of reverse information due to a read operation of another address is removed by driving the combined signal. Precharge completed [t=φ _L , φ _C
(OFF)], the potential of the sense node AB drops at the same potential due to the inflow of electron charge from the digit line D, and when the address signal and dummy address signal are driven [t = φ _W , φ _d (ON)] A differential voltage ΔV is obtained under the influence of the memory cell and the dummy cell. In this example, under the same conditions as the conventional circuit described above,
Generates a differential voltage of 0.4V or more. When the sense signal is driven [t=Q _S (ON)], the high potential sense node B becomes the potential of the digit line of this sense node example,
The low potential sense node A drops to the low potential (=OV) of the power supply together with the digit line D on the sense node side, and this low potential is written as an information signal to the memory cell at the address being read, and a refresh operation is performed. will be carried out. Also, before precharging is started again, the digit line D, in which high potential and low potential are clearly dispersed, or one of them,
Alternatively, information is read from the memory cell from a read circuit (not shown) connected to sense nodes A, B, or one of them, and then precharge is started again. In 1TR-RAM, the amount of charge to the capacitive element of the dummy cell is controlled during the precharge period, and this amount of charge is controlled so that the sense node B changes between the information "1" and "0" of the memory cell when driving a word signal. controlled by. That is, in the above explanation, the read operation of information "0" in which the node on the transistor side of the capacitive element _C1 of the memory cell shown in FIG. The characteristics of node A′ are shown.

Also, in the recently attempted 2TR-RAM, the first
The dummy address line and the address line in the figure are the same address line, and the memory cell and the dummy cell are composed of exactly the same transistor and capacitor, so the memory cell always contains information "1", "0" or Information “0” and “1” are accumulated. This 2TR
- Implementation of this invention in RAM reduces the capacitance value of the capacitive element of the memory cell that obtains the same voltage difference to less than half, and there is no need to control the charge during precharging of the dummy cell, resulting in extremely safe and reliable operation. You can get sex.

In both 1TR-RAM and 2TR-RAM, the invention achieves a balance between the digit lines extending on both sides of the sense circuit compared to conventional circuits, so the differential voltage at the sense node at the start of sensing is large, and the precharge time is also shortened. Reliable information reading is performed. According to this invention, the access time and cycle time of the conventional circuit example are 100nS and 170nS, respectively.
The time is reduced to 50nS and 120nS, and reading is possible even if the capacitance of the memory cell is reduced to 1/4.

Although the embodiments of the present invention have been described above, additions and changes to the present invention can be easily made as necessary. That is, the coupling transistor makes a pair of digit lines extending on both sides of the sense circuit conductive during precharging, and is an essential component of the present invention.In addition, other transistors whose gate electrodes are driven by the same coupling signal It is also possible to add , and connect its drain and source to two sense nodes, respectively.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is an operating waveform diagram of a conventional circuit, FIG. 3 is a drive signal waveform diagram of the embodiment of FIG. 1, and FIG. FIG. 3 is an operational waveform diagram of the embodiment. In the figure, 11 is an address line, 12 is a dummy address line, D is a digit line extending on both sides of the sense circuit, Q ₁ is a memory cell transistor, C ₁ is a memory cell capacitor, Q ₂ is a dummy cell transistor, C ₂ is the capacitive element of the dummy cell, Q ₃ , Q ₄
Q10 is a transistor that connects the digit line D, and the sense circuit, respectively, and _Q10 is the digit line D,
This is a transistor that connects

Claims (1)

[Claims] 1. A memory cell provided at each intersection of a plurality of word lines and a plurality of digit lines crossing these, and a pair of sense nodes connected to a pair of digit lines to which the memory cells are connected via a pair of transfer transistors. a sense circuit that performs a sensing operation in response to a sense control signal; a precharge circuit that supplies a precharge voltage to each of the pair of digit lines in response to a precharge signal; and a coupling transistor having an output region directly connected between the digit lines of the sense control signal, and stopping the sense control signal to make the coupling transistor conductive during precharging, and making the coupling transistor non-conductive after precharging to output the sense control signal. A memory integrated circuit, characterized in that the memory integrated circuit is configured to supply the sense circuit to the sense circuit.