JPS6149760B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a dynamic MOS memory circuit using an insulated gate field effect transistor (hereinafter referred to as a transistor).

Dynamic MOS memory circuits detect extremely small signals and discriminate information, and enable high-density integrated circuit configurations, so they require a memory circuit with a simple circuit configuration, low power consumption, and high detection sensitivity. shall be. This tendency is particularly noticeable in 1-transistor random access memory (1Tr-RAM), which uses transistors and capacitors as memory cells, and does not directly charge up the sense node of the sense amplifier as in conventional circuits. In the circuit configuration, power consumption due to static current is large, and in order to prevent this, an inconvenient circuit configuration is required for the integrated circuit configuration.

An object of the present invention is to provide a memory circuit with high sensitivity and low power consumption in a simple circuit.

The dynamic MOS memory circuit according to the present invention includes a pair of transistors 1 and 2 whose drains or sources and gates are cross-connected, a drive transistor 3 that pulls the common source of the transistors to a low potential, and a sense node of the pair of transistors. Transfer transistors 4 and 5 that control signal transmission between the pair A and B and the pair of digit lines D, and the digit line D at the time of reset, are connected to a power supply voltage at a low potential, preferably at a voltage approximately midway between the low potential power supply voltage and the power supply voltage. Transistors 6, 7 precharging to an intermediate voltage of the value
, charge-up transistors 8 and 9 that supply current from the power supply voltage to the digit line D after sensing starts, and memory cells 10 and 11 and dummy cells 12 and 12 connected to the respective digit lines.
13, the sense nodes A and B receive current supply during the precharge period and the read period through the transfer transistors 4 and 5.

Further, in the present invention, preferably, the memory cell and the dummy cell have substantially the same geometrical shape and are configured as an integrated circuit together with other circuit elements. Further, the transfer transistors 4 and 5 operate in the triode region before the start of sensing, and are driven by the signal φ _T that becomes a substantial reference potential during the period from the start of sensing to the completion of operation of the charge-up transistor, and one Preferably, the transistor is a depletion type transistor, which reenters the triode region as the sense node approaches the reference potential. In addition, the above sense nodes A and B and the input/output line I/O,
It is also a preferred embodiment of the present invention to provide transistors 22 and 23 that control coupling with O.

In the MOS memory circuit according to the present invention, precharging is performed using an intermediate potential, precharging and charging up of nodes can be easily performed using transfer transistors, and high-speed operation is possible.

As shown in FIG. 1, a memory circuit according to an embodiment of the present invention includes a pair of transistors 1 and 1, which are cross-connected such that their gates are coupled to the drains of the other transistors.
2, and a drive transistor 3 that lowers the common source node C of each transistor 1, 2 to a low potential after the start of sensing by the rise of the drive pulse φ _S. Sense nodes A and B, which are the drains corresponding to the crossing and connecting points of the pair of transistors 1 and 2, connect the drains and sources of the transfer transistors 4 and 5 whose gates are driven by the transfer pulse φ _T to the respective digit lines D. are connected via each. As described later, these transistors 4 and 5 are depletion type transistors that exhibit low impedance when the gate is set to a reference potential (GND), and in this embodiment, the gate has a value of -1.5V with respect to a power supply voltage of 5V. . All transistors in the circuit in this figure are N-channel MOS transistors,
It has an integrated circuit configuration. The digit line D is connected to the sources of transistors 6 and 7 whose drains are connected to an intermediate voltage source line V _p whose level is approximately 1/2 of the power source voltage V _p , and is precharged by a pulse φ _p applied to its gate. At this time, it is precharged by a power supply voltage V _p of approximately 2V, which is approximately intermediate to the power supply voltage. Also, when the transfer transistor is in the cutoff state after sensing starts, the 5V power supply voltage _D
In order to charge the digit line D, to a potential close to , the sources of charge-up transistors 8 and 9 whose gates are driven by the pulse φ _B are coupled to the respective digit line D, and the drains are connected to the power supply line V.
Connect to _D.

Memory cells 10, 11 and dummy cell 12,
In the integrated circuit configuration of this embodiment, 13 is a one-transistor type cell obtained in substantially the same geometric shape on the same surface of the silicon substrate. Transistors 14, 15, 16, 1 in each memory cell
In 7, the gate electrode is coupled to the word lines φ _Wi , φ _Wi+1 or the dummy word lines φ _DW , φ' _DW , one of the drain and source is connected to the digit line D, and the other common end is connected to the power supply line. It is connected to the other ends of capacitive elements 18, 19, 20, and 21 coupled to _VD .

In addition, the memory circuit of this embodiment allows for a charge increase after the start of sensing the digit line D, and in order to ensure high-speed access time characteristics,
A pair of input/output lines I/O for information signals are coupled to sense nodes A and B via transistors 22 and 23 whose gates are driven by a decode output control signal Y, respectively. cross-connected transistor 1,
The common source node C of the transistors 3 and 2 is connected to the transistor 3 whose potential is lowered by applying a pulse φ _S to the gate.
It is also coupled to the intermediate power supply line V _p through a transistor 24, which charges the sense node C to an intermediate potential by a precharge pulse φ _p .

FIG. 2 is an operational waveform diagram for better understanding the operation of the embodiment shown in FIG. As shown in this figure, in the embodiment of FIG. ₁ , _the digit lines _D ,
And sense nodes A and B are charged to about 2V. Since the precharge potential _Vp is lower than the power supply voltage _VD , the precharge time, ie, the reset time, can be shortened to 50 nS or less. When signal detection starts after the precharge period, the word line drive pulse φ _W and the dummy word line drive pulse φ _DW
becomes a high potential, the transistors of one memory cell and the other dummy cell of the digit line pair D extending from the sense amplifier become conductive, and the digit line potential changes in accordance with the charge of each capacitive element. The potentials of sense nodes A and B also change. Next, the transmission pulse φ _T falls to the reference potential, and the drive pulse φ _S gradually increases, thereby entering the sensing period t ₂ . Immediately after the start of sensing, both transfer transistors 4 and 5 are in a cutoff state, and only the potential difference between the pair of sense nodes A and B in the sense amplifier begins to be amplified. At this time, the charge up pulse φ _B is set to a high potential on the digit line pair D, thereby raising the digit line pair D to the power supply voltage V _p .
After the charging period _t3 for each of the digit line pairs ends, the potential of one of the sense nodes A and B falls, and one of the transfer transistors 4 and 5 coupled to this node becomes conductive, and the digit line pairs D, A current path is created from one of the sense nodes A and B to one of the sense nodes A and B. The high potential side of the sense node and the high potential side of the digit line are kept at a charged up potential, and during the refresh period _t4 after the transmission pulse φ _T is chained and becomes a high potential, the potentials of the digit line pair V _D , V ≦ produces a maximum amplitude between the reference potential O and the power supply potential V _D , and during this period, the control signal Y becomes high level at t ₄ and reading is performed. As the potential of the word line φ _W falls, the refresh period is completed, and refresh information is accumulated in the capacitor of the memory cell. The precharge period begins with the fall of the drive pulse φ _S and the rise of the precharge pulse φ _P , and within this period, the digit line pair D,
When the dummy word line is charged to an intermediate potential, the drive pulse φ _DW to the dummy word line falls, and the dummy cell refresh period _t5 ends.

During this operation period, the signal transmission to the input/output line is completed near the charge-up period because the capacitance of the sense node is extremely small compared to the digit line, and there is no delay in access time due to charge-up to the digit line. Also, since the transfer transistor is substantially cut off during the charge-up period to the digit line, no charge-up current flows through the sense amplifier, and there is no electrostatic loss in power consumption. Since the memory cell and the dummy cell are compared using the same capacitive element of the same shape, information detection with excellent balance and high sensitivity is realized.

In the above-described embodiment, it is also possible to provide input/output information from the digit line rather than from the sense node. Also, precharging to the common source node can be omitted if desired.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is an operational waveform diagram for explaining the operation of the embodiment of FIG. In the figure, 1, 2... A pair of cross-linked transistors in the sense amplifier, 3... A drive transistor that controls the potential of the common source node C, 4, 5... A digit line D, and sense nodes A, B. 6, 7...transistor for precharge, 8, 9...transistor for charge up, 10, 11...memory cell, 12, 13...
...dummy cell.

Claims (1)

[Claims] 1 A sense circuit having a pair of digit lines, a pair of flip-flop transistors whose gates and drains (or sources) are cross-connected at a pair of nodes, and whose sources (or drains) are commonly connected to a common node; means for precharging the pair of digit lines and the common node before starting sensing; means for energizing a dummy cell to write the precharged potential in the digit line to the dummy cell; and coupling the digit line and the pair of nodes. 1. A dynamic MOS memory circuit comprising a pair of depletion type transfer transistors, the gate of said transfer transistor being set to a potential lower than the potential of said precharged digit line at the start of sensing.