JPH0172655U - - Google Patents
Info
- Publication number
- JPH0172655U JPH0172655U JP1987168004U JP16800487U JPH0172655U JP H0172655 U JPH0172655 U JP H0172655U JP 1987168004 U JP1987168004 U JP 1987168004U JP 16800487 U JP16800487 U JP 16800487U JP H0172655 U JPH0172655 U JP H0172655U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- data
- error
- selects
- encoded data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
Description
第1図は本考案の一実施例を示すブロツク図、
第2図は書込み動作時の主動作を説明するための
タイミングチヤートである。
図中、1……タイミング発生回路、2……コマ
ンド保持回路、3……アドレス保持回路、4……
データ保持回路、5……符号化回路、6……メモ
リアレイ、7……第1の2―1セレクタ、8……
第2の2―1セレクタ、9……復号化回路、10
……誤りビツト検出回路、11……誤り表示信号
保持回路、12……誤り訂正回路、20……中央
演算処理装置(CPU)。
FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 2 is a timing chart for explaining the main operation during the write operation. In the figure, 1... timing generation circuit, 2... command holding circuit, 3... address holding circuit, 4...
Data holding circuit, 5... Encoding circuit, 6... Memory array, 7... First 2-1 selector, 8...
Second 2-1 selector, 9...decoding circuit, 10
...Error bit detection circuit, 11...Error display signal holding circuit, 12...Error correction circuit, 20...Central processing unit (CPU).
Claims (1)
部と、 書込み時は書込みデータを選択し、読出し時は
前記記憶部からの読出しデータを選択する第1の
選択回路と、 書込み時は前記符号化回路からの符号化データ
を選択し、読出し時は前記記憶部から読出した符
号化データを選択する第2の選択回路と、 前記第1及び第2の選択回路の出力データを復
号化する復号化回路と、 復号化データの誤りビツトを検出し、検出した
ならば誤り表示信号を出力する誤りビツト検出回
路と、 前記誤り表示信号を保持し、誤りビツトが発生
したことを外部論理装置に報知する誤り表示信号
保持回路とを備えた ことを特徴とする主記憶装置の試験装置。[Claims for Utility Model Registration] An encoding circuit that encodes written data; a storage section that stores written data and encoded data; and a system that selects written data when writing and reads from the storage section when reading. a first selection circuit that selects data; a second selection circuit that selects encoded data from the encoding circuit during writing, and selects encoded data read from the storage unit during reading; a decoding circuit that decodes the output data of the first and second selection circuits; an error bit detection circuit that detects error bits in the decoded data and outputs an error indication signal if detected; and the error indication signal. 1. A test device for a main memory device, comprising: an error display signal holding circuit for holding an error bit and notifying an external logic device that an error bit has occurred.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987168004U JPH0172655U (en) | 1987-11-02 | 1987-11-02 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987168004U JPH0172655U (en) | 1987-11-02 | 1987-11-02 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0172655U true JPH0172655U (en) | 1989-05-16 |
Family
ID=31456804
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987168004U Pending JPH0172655U (en) | 1987-11-02 | 1987-11-02 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0172655U (en) |
-
1987
- 1987-11-02 JP JP1987168004U patent/JPH0172655U/ja active Pending
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