JPH0179145U - - Google Patents
Info
- Publication number
- JPH0179145U JPH0179145U JP1987172651U JP17265187U JPH0179145U JP H0179145 U JPH0179145 U JP H0179145U JP 1987172651 U JP1987172651 U JP 1987172651U JP 17265187 U JP17265187 U JP 17265187U JP H0179145 U JPH0179145 U JP H0179145U
- Authority
- JP
- Japan
- Prior art keywords
- data
- master
- slave
- goes
- reading
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000009977 dual effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Hardware Redundancy (AREA)
- Detection And Correction Of Errors (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Description
第１図は本案の一実施例を示すブロツク線図、
第２図は動作説明図である。
１……マスタメモリパツケージ、２……スレイ
ブメモリパツケージ、３……アドレスカウンタ、
４……パツケージ選択回路、５……書込／読出制
御回路、６……冗長ビツト生成回路、７……デー
タ訂正チエツク回路、８……マスター、スレイブ
切替回路。
FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 2 is an explanatory diagram of the operation. 1...Master memory package, 2...Slave memory package, 3...Address counter,
4...Package selection circuit, 5...Write/read control circuit, 6...Redundant bit generation circuit, 7...Data correction check circuit, 8...Master/slave switching circuit.
Claims (1)
データと冗長ビツトからデータの誤りを訂正また
は訂正不可エラーを検出するデータ訂正チエツク
回路をもつバツフアメモリに於いて、マスター、
スレイブの２重化構成とした記憶部とデータ訂正
チエツク回路からの訂正不可エラー信号で反転動
作するマスター、スレイブ切替回路をもち、書込
時は両記憶部へ、読出時はマスター、スレイブの
一方からのデータを読出し、データの訂正不可の
時他方へ切替えながら読出動作を続行することを
特徴とする高信頼性バツフアメモリ。 In a buffer memory that has a data correction check circuit that writes data with redundant bits added to it and corrects data errors or detects uncorrectable errors from the data and redundant bits when reading, the master,
It has a storage section with a dual slave configuration and a master/slave switching circuit that performs inversion operation based on an uncorrectable error signal from the data correction check circuit.When writing, it goes to both storage sections, and when reading, it goes to either the master or slave. 1. A highly reliable buffer memory characterized in that when data cannot be corrected, the read operation is continued while switching to the other mode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987172651U JPH0179145U (en) | 1987-11-13 | 1987-11-13 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987172651U JPH0179145U (en) | 1987-11-13 | 1987-11-13 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0179145U true JPH0179145U (en) | 1989-05-26 |
Family
ID=31464609
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987172651U Pending JPH0179145U (en) | 1987-11-13 | 1987-11-13 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0179145U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012203642A (en) * | 2011-03-25 | 2012-10-22 | Mega Chips Corp | Memory system |
-
1987
- 1987-11-13 JP JP1987172651U patent/JPH0179145U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012203642A (en) * | 2011-03-25 | 2012-10-22 | Mega Chips Corp | Memory system |
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