JPH0174671U - - Google Patents
Info
- Publication number
- JPH0174671U JPH0174671U JP1987171165U JP17116587U JPH0174671U JP H0174671 U JPH0174671 U JP H0174671U JP 1987171165 U JP1987171165 U JP 1987171165U JP 17116587 U JP17116587 U JP 17116587U JP H0174671 U JPH0174671 U JP H0174671U
- Authority
- JP
- Japan
- Prior art keywords
- vertical
- pulse
- period
- whose
- coincides
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 238000000034 method Methods 0.000 claims 1
- 238000003786 synthesis reaction Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Details Of Television Scanning (AREA)
Description
第１図は、この考案の垂直帰線消去回路を適用
したＣＲＴデイスプレイ装置の一実施例を示す回
路図、第２図は、第１図に示した回路各部の信号
波形図、第３図は、従来の垂直帰線消去回路を適
用したＣＲＴデイスプレイ装置の一例を示す回路
図、第４図は、第３図に示した回路各部の信号波
形図である。
２……パーソナルコンピユータ、３……ＣＲＴ
デイスプレイ装置、１１……垂直帰線消去回路、
１２……保護回路。
FIG. 1 is a circuit diagram showing an embodiment of a CRT display device to which the vertical blanking circuit of this invention is applied, FIG. 2 is a signal waveform diagram of each part of the circuit shown in FIG. 1, and FIG. , a circuit diagram showing an example of a CRT display device to which a conventional vertical blanking circuit is applied; FIG. 4 is a signal waveform diagram of each part of the circuit shown in FIG. 3; 2...Personal computer, 3...CRT
Display device, 11... Vertical blanking circuit,
12...Protection circuit.
Claims (1)
の始期に一致する負極性の垂直同期パルスと、こ
の垂直同期パルスから垂直偏向電流を生成する過
程で形成され、その後縁部が垂直帰線期間の終期
に一致する垂直出力パルスとを論理合成し、垂直
帰線消去パルスを形成する垂直帰線消去回路であ
つて、前記垂直同期パルスの供給が断たれたとき
に、消滅時点で等価的に極性が負固定されてしま
う垂直同期パルスとの前記論理合成を禁止し、少
なくも垂直出力パルス期間だけは垂直帰線消去パ
ルスを形成する保護回路を設けてなる垂直帰線消
去回路。 A vertical sync pulse of negative polarity is supplied from the outside and whose leading edge coincides with the beginning of the vertical retrace period, and is formed in the process of generating a vertical deflection current from this vertical sync pulse, whose trailing edge coincides with the start of the vertical retrace period. A vertical blanking circuit that logically synthesizes a vertical output pulse that coincides with the end of a period to form a vertical blanking pulse, and when the supply of the vertical synchronizing pulse is cut off, an equivalent The vertical blanking circuit is provided with a protection circuit which prohibits the logic synthesis with the vertical synchronizing pulse whose polarity is fixed to a negative value and forms a vertical blanking pulse at least during the vertical output pulse period.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987171165U JPH0174671U (en) | 1987-11-09 | 1987-11-09 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987171165U JPH0174671U (en) | 1987-11-09 | 1987-11-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0174671U true JPH0174671U (en) | 1989-05-19 |
Family
ID=31462752
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987171165U Pending JPH0174671U (en) | 1987-11-09 | 1987-11-09 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0174671U (en) |
-
1987
- 1987-11-09 JP JP1987171165U patent/JPH0174671U/ja active Pending