JPS647356U - - Google Patents
Info
- Publication number
- JPS647356U JPS647356U JP9945787U JP9945787U JPS647356U JP S647356 U JPS647356 U JP S647356U JP 9945787 U JP9945787 U JP 9945787U JP 9945787 U JP9945787 U JP 9945787U JP S647356 U JPS647356 U JP S647356U
- Authority
- JP
- Japan
- Prior art keywords
- parity
- received data
- storage device
- detect
- parity check
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Detection And Correction Of Errors (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Description
第１図は本考案の実施例のブロツク図、第２図
は本考案の実施例のパリテイ検査部におけるタイ
ミングチヤート、第３図は従来の不揮発性メモリ
ＩＣのブロツク図である。
１……不揮発性メモリ、２……データレジスタ
、３……インストラクシヨンデコードロジツク、
４……クロツクジエネレータ、５……アドレスデ
コーダ、６……出力バツフア、７……パリテイ検
査部。
FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a timing chart of a parity check section of an embodiment of the present invention, and FIG. 3 is a block diagram of a conventional nonvolatile memory IC. 1...Non-volatile memory, 2...Data register, 3...Instruction decode logic,
4... Clock generator, 5... Address decoder, 6... Output buffer, 7... Parity check section.
Claims (1)
装置であつて、 不揮発性記憶装置と、受信データのパリテイ検
査を行つてパリテイエラーを検出するパリテイ検
査部と、上記パリテイ検査部がパリテイエラーを
検出したときに上記不揮発性記憶装置に受信デー
タの書き込みを行わず、パリテイ検査部がパリテ
イエラーを検出しないときに受信データを不揮発
性記憶装置に書き込む書込み制御部とを備えたこ
とを特徴とする受信データ記録装置。[Scope of Claim for Utility Model Registration] A device for receiving data with parity bits added thereto, comprising: a non-volatile storage device; a parity check unit that performs a parity check on the received data to detect parity errors; and the above-mentioned parity check. a write control section that does not write the received data to the nonvolatile storage device when the parity checking section detects a parity error, and writes the received data to the nonvolatile storage device when the parity checking section does not detect a parity error; A received data recording device comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9945787U JPS647356U (en) | 1987-06-30 | 1987-06-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9945787U JPS647356U (en) | 1987-06-30 | 1987-06-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS647356U true JPS647356U (en) | 1989-01-17 |
Family
ID=31326633
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9945787U Pending JPS647356U (en) | 1987-06-30 | 1987-06-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS647356U (en) |
-
1987
- 1987-06-30 JP JP9945787U patent/JPS647356U/ja active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS59185097A (en) | Memory device with self-diagnostic function | |
| JP2023090690A (en) | Circuit and method for reading ECC from memory | |
| FI893656A0 (en) | FOERFARANDE FOER FOERHINDRANDE AV FEL I MINNESSYSTEM FOER DATABEARBETNINGSANLAEGGNINGAR, SAERSKILT TELEFONFOERMEDLINGSANLAEGGNINGAR. | |
| JPH0179145U (en) | ||
| JPS5870500A (en) | Semiconductor storing circuit | |
| JPS61246997A (en) | Electrically erasable and rewritable read only memory | |
| JPS6296744U (en) | ||
| JP2025084720A (en) | Method, device and system for serial bus transactions with selectable data transaction size - Patents.com | |
| JPH0474340U (en) | ||
| JP2811728B2 (en) | Input/Output Control Unit | |
| JPS60174957U (en) | Memory device function confirmation circuit | |
| JPS62187350U (en) | ||
| JPS6170243U (en) | ||
| JPS58118599U (en) | Storage device | |
| JPS63170756A (en) | Main memory initialization method | |
| JPS63175250U (en) | ||
| JPS62198600U (en) | ||
| JPH0197498U (en) | ||
| JPH0478654U (en) | ||
| JPS58148798U (en) | memory element | |
| JPS6116648U (en) | Microprogram-controlled information processing device | |
| JPH0172655U (en) | ||
| JPH0289669U (en) | ||
| JPS6488641A (en) | Information processor | |
| JPS59168900U (en) | Program memory failure detection circuit |