JPH0183350U - - Google Patents
Info
- Publication number
- JPH0183350U JPH0183350U JP1987178058U JP17805887U JPH0183350U JP H0183350 U JPH0183350 U JP H0183350U JP 1987178058 U JP1987178058 U JP 1987178058U JP 17805887 U JP17805887 U JP 17805887U JP H0183350 U JPH0183350 U JP H0183350U
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- capacitive element
- conductive layer
- layer
- stacked
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 description 1
Landscapes
- Semiconductor Memories (AREA)
- Dram (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
第１図及び第２図は本考案の一実施例を示して
おり、第１図は第２図の―線における側断面
図、第２図は平面図である。第３図〜第５図は本
考案の先願に開示されている例を示しており、第
３図は第４図の―線における側断面図、第４
図は平面図、第５図は製造工程を順次に示す側断
面図である。
なお図面に用いた符号において、２３ａ，２３
ｂ……電極、３２ａ，３２ｂ……メモリセル、３
４ａ，３４ｂ……容量素子、である。
1 and 2 show an embodiment of the present invention, in which FIG. 1 is a side sectional view taken along the line --- in FIG. 2, and FIG. 2 is a plan view. 3 to 5 show an example disclosed in the earlier application of the present invention, and FIG. 3 is a side sectional view taken along the line --- in FIG.
The figure is a plan view, and FIG. 5 is a side sectional view sequentially showing the manufacturing process. In addition, in the symbols used in the drawings, 23a, 23
b...electrode, 32a, 32b...memory cell, 3
4a, 34b... Capacitive elements.
Claims (1)
用いてメモリセルが構成されており、前記容量素
子の一方の電極は前記トランジスタの一方のソー
ス・ドレイン領域に接続されており、前記容量素
子の他方の電極は誘電体層を介して前記一方の電
極上に積層されているメモリ装置において、 互いに隣接している２つのメモリセルの一方に
おける前記容量素子の前記一方の電極が第１の導
電層で形成されており、 前記２つのメモリセルの他方における前記容量
素子の前記一方の電極が前記第１の導電層とは異
なる層である第２の導電層で形成されており、 前記第１及び第２の導電層が少なくともそれら
の端部において互いに重畳していることを特徴と
するメモリ装置。[Claims for Utility Model Registration] A memory cell is configured using a switching transistor and a capacitive element, one electrode of the capacitive element is connected to one source/drain region of the transistor, In a memory device in which the other electrode of the capacitive element is stacked on the one electrode via a dielectric layer, the one electrode of the capacitive element in one of two memory cells adjacent to each other is stacked on the one electrode via a dielectric layer. one conductive layer, the one electrode of the capacitive element in the other of the two memory cells is formed of a second conductive layer that is a different layer from the first conductive layer, A memory device characterized in that the first and second conductive layers overlap each other at least at their ends.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987178058U JPH0617320Y2 (en) | 1987-11-21 | 1987-11-21 | Memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987178058U JPH0617320Y2 (en) | 1987-11-21 | 1987-11-21 | Memory device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0183350U true JPH0183350U (en) | 1989-06-02 |
| JPH0617320Y2 JPH0617320Y2 (en) | 1994-05-02 |
Family
ID=31469692
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987178058U Expired - Lifetime JPH0617320Y2 (en) | 1987-11-21 | 1987-11-21 | Memory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0617320Y2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3394728B2 (en) * | 1999-06-21 | 2003-04-07 | 株式会社日新 | Case |
-
1987
- 1987-11-21 JP JP1987178058U patent/JPH0617320Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0617320Y2 (en) | 1994-05-02 |
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