JPH01873A - playback device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an apparatus for reproducing a video signal digitized and recorded on a recording medium, such as a reproducing apparatus such as a reproducing side of a digital VTR.

Prior Art FIG. 5 shows an example of a block diagram of a conventional playback device using a two-field memory. In the figure, digital data reproduced from 7 is written into field memories 1 and 2, and read digital data is output from 8. Write control of the field memory 1.2 is performed by a write control circuit 18, and read control is performed by a read control circuit 17. Further, the write address generation circuit 6 inputs an output 14 (hereinafter referred to as ID) obtained by reproducing an address recorded in advance for each block, and generates a write address WA for the memory 1.2. do. The read address generation circuit 5 receives the video synchronization signal 12 and generates a memory read address RA. The read enable signals RE1 and RE2 are output from the read control circuit 17 and manually input to the respective memories 1 and 2.

One of the two read enable signals RE1 and RE2 is at H level, and the read enable signals RE1 and RE2 alternately go to H level at a period corresponding to the playback speed. When read enable signals REI and RE2 are at H level, digital data 8 indicated by read address RA is output from the respective memories. The write control signals WS1 and WS2 are output from the write control circuit 18 and indicate whether each block of the reproduced digital data 7 is writable or not, and when the block is at H level, it is writable. be. In order to prevent conflicts between writing and reading each memory, the read enable signal is logically negated, and
A logic bond with the write control signal is taken, and write enables WEI and WB2 are set. These write enable signals W E 1 and W E 2 are input to each corresponding memory 1.2, and when they are at H level, the reproduced digital data 7 is transferred to the location indicated by the write address WA of the corresponding memory. The value is written.

A detailed block diagram of the read control circuit is shown in FIG.

The readout control circuit 17 operates at a playback speed of 1/S (
For convenience of explanation, -1>S, or S≧+1. The main purpose of the present invention is to change the switching period of the two memories 1.2 by S (S is an integer). The variable frequency divider circuit 171 receives a field pulse 9 representing the beginning of the field period in the read example and a double speed mode signal 10 which is a signal indicating the value of S.
is input, field pulse 9 is frequency-divided by S, and D
Outputs the flip-flop clock 173. It also outputs a write center pulse 174 as shown in FIG. 6(1). The D flip-flop 172 has a clock 173.
is input, and read enable signals RE1 and RE2 as shown in FIGS. 6(B) and 6(C) are output. One of the enable signals REI and RE2 is at the H level and alternately becomes the H level, so that the corresponding memory becomes in the read state. Initialization timing pulse WINIT is synchronized with read enable signal REI and write center pulse 17.
4 and is used to initialize the write control circuit. By the operation of these read control circuits 17, for example, when the speed is 1/2,
Data for one field is read continuously for two field periods, and when the speed is 174 times, it is read continuously for four field periods, and as a result, an image corresponding to the playback speed is output. FIG. 8 is a block diagram of the write control circuit 18, in which the D flip 70 blocks 181 and 182 each hold field numbers WSCi to WSe2 to be written to the corresponding memories.

The output of this D flip-flop is
6. ID that enters 187 and represents the field of playback data
13 (hereinafter referred to as field ID), and if they are the same value, the corresponding write control signal WS1. WS
2 becomes H level. For example, during forward slow playback and when the first field is being read from the memory 1 (T1 in FIG. 11), the first field is controlled to be written to the memory 2. By doing this, when the readout is subsequently transferred to the memory 2, field 1 is read out and continuous images reproduced in forward slow motion are output. Therefore, the value WSCI of the D flip-flop 70 block 181 is O, and the value WSC2 of the D flip-flop 182 is 1 (T1G in FIG. 11). WSCI, WSe for forward playback
The value of 2 is WSC1=(WSC2+1) MOD 4
WSC2=(WSC1+1.) MOD 4, and in the case of reverse playback, WSC1=(WSe2-1) MOD 4WSC2
= (WSCI-1) MOD 4. (A MOD B) here represents the remainder when A is divided by B.

Based on these factors, data to be written to memory is selected. There is also an initialization circuit 185 to match the timing of the reproduced data and the write. Initialization circuit 1
85 is when the memory 1 is being written and the initialization timing pulse WINIT is at H level, and the reproduced data and the output of the D flip-flop 181 WSC
, 1 are not the same, by directly setting the field ID to the D flip 70 tab, the phase of the forcibly reproduced data and WSCI, WSe27 are matched.

Problems to be Solved by the Invention In the conventional reproducing apparatus configured as described above, readout is controlled only by the double speed mode signal 10 regardless of the reproduced data 7.
If the relationship between 0 and the reproduced data 7 does not completely match, the image may skip or go back, or the reproduced data of the two fields may be mixed, making it impossible to obtain a good reproduced image. There wasn't. For example, this is a transient state when the playback speed 1/S changes continuously, when S is other than an integer, or when it changes. In such a case, it is not possible to completely match the relationship between the double speed mode signal and the reproduced data. In view of this point, the present invention aims to obtain smooth and good reproduced images even when the reproduction speed changes continuously or in a transient state when it changes.

Means for Solving the Problems The reproducing apparatus according to the present invention is characterized in that the writing status is determined based on the reproduced ID and a signal that distinguishes the reproduction direction, and the read control circuit and the write control circuit are controlled. It is something.

Effects According to the present invention, good reproduced images can be continuously obtained even when the reproduction speed changes continuously.

Embodiment FIG. 1 shows a block diagram of a reproducing apparatus in an embodiment of the present invention. FIG. 2 shows a signal timing diagram. In FIG. 1, the points that are different from the conventional example shown in FIG. 10 will be mainly explained. The field pulse 9 and the EOF pulse 16 are input to the read control circuit No. 3, and read enable signals REI and RE2 are output. REI, R
When E2 is at H level, data 8 is read from the address indicated by RA of the memory 1.2 corresponding to them.

EOF pulse 16 is a timing pulse that represents the end of a field of recovered data. In other words, when this pulse is issued, it means that all the data in the field where the command has been written has been written, and with the next field pulse 9, REI and RE2 are inverted, and the memory where data 7 was written until now is is switched to reading, and the memory from which data 8 was being read is switched to writing (example: 2nd drawing period 2). If the next field pulse enters after the EOF pulse 16 is output, the read control circuit 3 maintains the previous state and does not switch between writing and reading the memory (for example, the second field pulse). Arts and crafts period 3). The EOF pulse decoder 15 has ID1
4 and a control signal 11 representing forward/reverse direction, an EOF pulse and a value 17 (hereinafter SCT) representing the ID field number at that time corresponding to the EOF pulse are input.
) is output. FIG. 3 shows a detailed block diagram of the EOF pulse decoder. In FIG. 3, 151 is a field end detection circuit in the forward and reverse directions, which detects an ID between two preset values min and max, and when an ID corresponding to that appears, 153 (
A high level pulse) is output. Also, min and max take different values for forward and reverse playback, and are switched by switches 155 and 156 using the forward/reverse signal 11.
In the case of the forward direction, f w d min and fwdmax are selected, and in the case of the reverse direction, rev min and revmax are selected. In the forward/reverse change detection circuit 152, when the forward/reverse signal 11 changes, the circuit 154 is reset to the L level, and when the pulse 153 is input, the circuit 154 is set to the H level. This forward/reverse change detection circuit 15
2 output 154 and field end detection circuit output 153
is input to the AND circuit 157 and becomes the EOF pulse 16. Due to the operation of these circuits, even if 153 pulses are output, only once after the playback direction has changed, the EO
F pulse 16 is not output. field decoder 15
9 inputs ID14 and decodes it into a field number. The output of this field decoder 159 is input to a D flip-flop 158 and latched by the EOF pulse 16 to become 5CT17. Figure 4 (A) shows the track trajectory and head trajectory on the tape when recording one field divided into 2.5 tracks, and Figure 4 (B)
is a timing diagram of reproduced data. The operation of the field end detection circuit 151 will be explained in detail using FIG. 4. All numbers in FIG. 4 represent field numbers. a, b, c, d in Fig. 4 (A) are positive direction 1
Head trajectory during 774x playback, a, b, c, d
We are tracing in the order of (.First, when the head trajectory is a,
Data of field number O is reproduced as in period a in FIG. 4(B). The same applies to b. At the time of C, Fig. 4 (
As in period C of B), field number O is first played, and field number 1 is played from the middle. Here, point X in FIG. 4(A) is the data of field number 1,
and is the first data block of that field, and when point X is first played back (period C Xi in FIG. 4(B))
, all the data of field number O has already been traced and reproduced by the head. Therefore, during forward playback, the field end detection circuit 151 in FIG. A pulse is output from 153 when D14 is regenerated. In order to select these IDs, set values fwdmin and fwdmax are appropriately selected. Even in the case of reverse playback, it can be said that when a certain ID is played back, all the fields immediately before it have been played back. However, since the slope of the head trajectory is opposite to that in the forward direction, set values revmin and revmax are used that are different from those for forward playback. Here, we have explained the case where one field is divided into 2.5 tracks and recorded, but no matter how many fields are divided and no matter where on the track the beginning of the field is,
You can detect the end of a field in a similar way. Returning to FIG. 1, the write control circuit 4 inputs the 5CT 17 and the forward/reverse signal 11, and outputs the write control signals WSI and WS2. Since the field to be written is determined based on the SCT, the reproduced data is written without waste.

This embodiment is an example in which one field is divided into 2.5 tracks and recorded, and the playback speed and the readout side and the phase 6 of the reproduced data (, no matter how, It is possible to obtain continuous and smooth reproduced images without jumps.Also, in this embodiment, a 2-field memory is used, but the same effect can be obtained without being limited to this.Also, in this embodiment, the writing Although field numbers are used for control, the same effect can be achieved without being limited to this.

As described in detail, according to the present invention, when a certain block is recorded with an address assigned to it and is played back at an arbitrary playback speed n (-1<n≦+1). You can obtain continuous, good images with no image skipping, even when
Its practical effects are great.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a playback device according to an embodiment of the present invention, FIG. 2 is a timing diagram of the above embodiment, and FIG.
A detailed block diagram of the F-pulse decoder 15, FIG.
FIG. 5 is a block diagram of a playback device in a conventional embodiment. FIG. 6 is a timing diagram of a playback device in a conventional embodiment. A detailed block diagram of the read control circuit 17, and FIG. 8 is a detailed block diagram of the write control circuit 18. 1.2... Field memory, 3... Read control circuit, 4... Write control circuit, 5... Read address generation circuit, 6... Write address generation circuit,
15...EOF decoder. Name of agent: Patent attorney Toshio Nakao and one other person ^hehehehehehe<
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Claims (1)

[Claims] A playback device that writes and reads data recorded on a recording medium by adding an address to each block of a certain size to a memory during playback, and checks whether a predetermined writing period has ended or not. A playback device characterized in that the switching timing between writing and reading of the memory is controlled by making a judgment based on the address.